usrp3: Added AXI DMA FIFO control core

- Can access all registers in axi_dma_fifo.v

3 files changed, 382 insertions, 0 deletions

diff --git a/host/lib/usrp/cores/CMakeLists.txt b/host/lib/usrp/cores/CMakeLists.txt
index f28ae040f..744d5398e 100644
--- a/host/lib/usrp/cores/CMakeLists.txt
+++ b/host/lib/usrp/cores/CMakeLists.txt
@@ -40,4 +40,5 @@ LIBUHD_APPEND_SOURCES(
     ${CMAKE_CURRENT_SOURCE_DIR}/rx_dsp_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/tx_dsp_core_3000.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/radio_ctrl_core_3000.cpp
+    ${CMAKE_CURRENT_SOURCE_DIR}/dma_fifo_core_3000.cpp
 )
diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.cpp b/host/lib/usrp/cores/dma_fifo_core_3000.cpp
new file mode 100644
index 000000000..28a495431
--- /dev/null
+++ b/host/lib/usrp/cores/dma_fifo_core_3000.cpp
@@ -0,0 +1,305 @@
+//
+// Copyright 2015 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "dma_fifo_core_3000.hpp"
+#include <uhd/exception.hpp>
+#include <boost/thread/thread.hpp> //sleep
+#include <uhd/utils/soft_register.hpp>
+#include <uhd/utils/msg.hpp>
+
+using namespace uhd;
+
+#define SR_DRAM_BIST_BASE 16
+
+dma_fifo_core_3000::~dma_fifo_core_3000(void) {
+    /* NOP */
+}
+
+class dma_fifo_core_3000_impl : public dma_fifo_core_3000
+{
+protected:
+    class rb_addr_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(ADDR, /*width*/ 3, /*shift*/ 0);  //[2:0]
+
+        static const boost::uint32_t RB_FIFO_STATUS     = 0;
+        static const boost::uint32_t RB_BIST_STATUS     = 1;
+        static const boost::uint32_t RB_BIST_XFER_CNT   = 2;
+        static const boost::uint32_t RB_BIST_CYC_CNT    = 3;
+
+        rb_addr_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + 0)
+        {
+            //Initial values
+            set(ADDR, RB_FIFO_STATUS);
+        }
+    };
+
+    class bist_ctrl_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(GO,               /*width*/ 1, /*shift*/ 0);  //[0]
+        UHD_DEFINE_SOFT_REG_FIELD(CONTINUOUS_MODE,  /*width*/ 1, /*shift*/ 1);  //[1]
+        UHD_DEFINE_SOFT_REG_FIELD(TEST_PATT,        /*width*/ 2, /*shift*/ 4);  //[5:4]
+
+        static const boost::uint32_t TEST_PATT_ZERO_ONE     = 0;
+        static const boost::uint32_t TEST_PATT_CHECKERBOARD = 1;
+        static const boost::uint32_t TEST_PATT_COUNT        = 2;
+        static const boost::uint32_t TEST_PATT_COUNT_INV    = 3;
+
+        bist_ctrl_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + SR_DRAM_BIST_BASE + 0)
+        {
+            //Initial values
+            set(GO, 0);
+            set(CONTINUOUS_MODE, 0);
+            set(TEST_PATT, TEST_PATT_ZERO_ONE);
+        }
+    };
+
+    class bist_cfg_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(MAX_PKTS,         /*width*/ 18, /*shift*/ 0);  //[17:0]
+        UHD_DEFINE_SOFT_REG_FIELD(MAX_PKT_SIZE,     /*width*/ 13, /*shift*/ 18); //[30:18]
+        UHD_DEFINE_SOFT_REG_FIELD(PKT_SIZE_RAMP,    /*width*/ 1,  /*shift*/ 31); //[31]
+
+        bist_cfg_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + SR_DRAM_BIST_BASE + 4)
+        {
+            //Initial values
+            set(MAX_PKTS, 0);
+            set(MAX_PKT_SIZE, 0);
+            set(PKT_SIZE_RAMP, 0);
+        }
+    };
+
+    class bist_delay_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(TX_PKT_DELAY,     /*width*/ 16, /*shift*/ 0);  //[15:0]
+        UHD_DEFINE_SOFT_REG_FIELD(RX_SAMP_DELAY,    /*width*/  8, /*shift*/ 16); //[23:16]
+
+        bist_delay_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + SR_DRAM_BIST_BASE + 8)
+        {
+            //Initial values
+            set(TX_PKT_DELAY, 0);
+            set(RX_SAMP_DELAY, 0);
+        }
+    };
+
+    class bist_sid_reg_t : public soft_reg32_wo_t {
+    public:
+        UHD_DEFINE_SOFT_REG_FIELD(SID,     /*width*/ 32, /*shift*/ 0);  //[31:0]
+
+        bist_sid_reg_t(boost::uint32_t base):
+            soft_reg32_wo_t(base + SR_DRAM_BIST_BASE + 12)
+        {
+            //Initial values
+            set(SID, 0);
+        }
+    };
+
+public:
+    class fifo_readback {
+    public:
+        fifo_readback(wb_iface::sptr iface,  const size_t base, const size_t rb_addr) :
+            _iface(iface), _addr_reg(base), _rb_addr(rb_addr)
+        {
+            _addr_reg.initialize(*iface, true);
+        }
+
+        bool is_fifo_instantiated() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_FIFO_STATUS);
+            return _iface->peek32(_rb_addr) & 0x80000000;
+        }
+
+        boost::uint32_t get_occupied_cnt() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_FIFO_STATUS);
+            return _iface->peek32(_rb_addr) & 0x1FFFFF;
+        }
+
+        struct bist_status_t {
+            bool running;
+            bool finished;
+            boost::uint8_t error;
+        };
+
+        bist_status_t get_bist_status() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_STATUS);
+            boost::uint32_t st32 = _iface->peek32(_rb_addr) & 0xF;
+            bist_status_t status;
+            status.running = st32 & 0x1;
+            status.finished = st32 & 0x2;
+            status.error = static_cast<boost::uint8_t>((st32>>2) & 0x3);
+            return status;
+        }
+
+        bool is_ext_bist_supported() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_STATUS);
+            return _iface->peek32(_rb_addr) & 0x80000000;
+        }
+
+        double get_xfer_ratio() {
+            boost::lock_guard<boost::mutex> lock(_mutex);
+            boost::uint32_t xfer_cnt = 0, cyc_cnt = 0;
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_XFER_CNT);
+            xfer_cnt = _iface->peek32(_rb_addr);
+            _addr_reg.write(rb_addr_reg_t::ADDR, rb_addr_reg_t::RB_BIST_CYC_CNT);
+            cyc_cnt = _iface->peek32(_rb_addr);
+            return (static_cast<double>(xfer_cnt)/cyc_cnt);
+        }
+
+    private:
+        wb_iface::sptr  _iface;
+        rb_addr_reg_t   _addr_reg;
+        const size_t    _rb_addr;
+        boost::mutex    _mutex;
+    };
+
+public:
+    dma_fifo_core_3000_impl(wb_iface::sptr iface, const size_t base, const size_t readback):
+        _iface(iface), _base(base), _fifo_readback(iface, base, readback),
+        _bist_ctrl_reg(base), _bist_cfg_reg(base), _bist_delay_reg(base), _bist_sid_reg(base)
+    {
+        _bist_ctrl_reg.initialize(*iface, true);
+        _bist_cfg_reg.initialize(*iface, true);
+        _has_ext_bist = _fifo_readback.is_ext_bist_supported();
+        if (_has_ext_bist) {
+            _bist_delay_reg.initialize(*iface, true);
+            _bist_sid_reg.initialize(*iface, true);
+        }
+    }
+
+    virtual boost::uint32_t get_occupied_cnt() {
+        return _fifo_readback.get_occupied_cnt();
+    }
+
+    virtual bool ext_bist_supported() {
+        return _fifo_readback.is_ext_bist_supported();
+    }
+
+    virtual boost::uint8_t run_bist(bool finite = true, boost::uint32_t timeout_ms = 500) {
+        return run_ext_bist(finite, 0, 0, 0, timeout_ms);
+    }
+
+    virtual boost::uint8_t run_ext_bist(
+        bool finite,
+        boost::uint32_t rx_samp_delay,
+        boost::uint32_t tx_pkt_delay,
+        boost::uint32_t sid,
+        boost::uint32_t timeout_ms = 500
+    ) {
+        boost::lock_guard<boost::mutex> lock(_mutex);
+
+        _wait_for_bist_done(timeout_ms, true);          //Stop previous BIST and wait (if running)
+        _bist_ctrl_reg.write(bist_ctrl_reg_t::GO, 0);   //Reset
+
+        _bist_cfg_reg.set(bist_cfg_reg_t::MAX_PKTS, (2^18)-1);
+        _bist_cfg_reg.set(bist_cfg_reg_t::MAX_PKT_SIZE, 8000);
+        _bist_cfg_reg.set(bist_cfg_reg_t::PKT_SIZE_RAMP, 0);
+        _bist_cfg_reg.flush();
+
+        if (_has_ext_bist) {
+            _bist_delay_reg.set(bist_delay_reg_t::RX_SAMP_DELAY, rx_samp_delay);
+            _bist_delay_reg.set(bist_delay_reg_t::TX_PKT_DELAY, tx_pkt_delay);
+            _bist_delay_reg.flush();
+
+            _bist_sid_reg.write(bist_sid_reg_t::SID, sid);
+        } else {
+            if (rx_samp_delay != 0 || tx_pkt_delay != 0 || sid != 0) {
+                throw uhd::not_implemented_error(
+                    "dma_fifo_core_3000: Runtime delay and SID support only available on FPGA images with extended BIST enabled");
+            }
+        }
+
+        _bist_ctrl_reg.set(bist_ctrl_reg_t::TEST_PATT, bist_ctrl_reg_t::TEST_PATT_COUNT);
+        _bist_ctrl_reg.set(bist_ctrl_reg_t::CONTINUOUS_MODE, finite ? 0 : 1);
+        _bist_ctrl_reg.write(bist_ctrl_reg_t::GO, 1);
+
+        if (!finite) {
+            boost::this_thread::sleep(boost::posix_time::milliseconds(timeout_ms));
+        }
+
+        _wait_for_bist_done(timeout_ms, !finite);
+        if (!_fifo_readback.get_bist_status().finished) {
+            throw uhd::runtime_error("dma_fifo_core_3000: DRAM BIST state machine is in a bad state.");
+        }
+
+        return _fifo_readback.get_bist_status().error;
+    }
+
+    virtual double get_bist_throughput(double fifo_clock_rate) {
+        if (_has_ext_bist) {
+            _wait_for_bist_done(1000);
+            static const double BYTES_PER_CYC = 8;
+            return _fifo_readback.get_xfer_ratio() * fifo_clock_rate * BYTES_PER_CYC;
+        } else {
+            throw uhd::not_implemented_error(
+                "dma_fifo_core_3000: Throughput counter only available on FPGA images with extended BIST enabled");
+        }
+    }
+
+private:
+    void _wait_for_bist_done(boost::uint32_t timeout_ms, bool force_stop = false)
+    {
+        boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
+        boost::posix_time::time_duration elapsed;
+
+        while (_fifo_readback.get_bist_status().running) {
+            if (force_stop) {
+                _bist_ctrl_reg.write(bist_ctrl_reg_t::GO, 0);
+                force_stop = false;
+            }
+            boost::this_thread::sleep(boost::posix_time::microsec(1000));
+            elapsed = boost::posix_time::microsec_clock::local_time() - start_time;
+            if (elapsed.total_milliseconds() > timeout_ms) break;
+        }
+    }
+
+private:
+    wb_iface::sptr  _iface;
+    const size_t    _base;
+    boost::mutex    _mutex;
+    bool            _has_ext_bist;
+
+    fifo_readback       _fifo_readback;
+    bist_ctrl_reg_t     _bist_ctrl_reg;
+    bist_cfg_reg_t      _bist_cfg_reg;
+    bist_delay_reg_t    _bist_delay_reg;
+    bist_sid_reg_t      _bist_sid_reg;
+};
+
+//
+// Static make function
+//
+dma_fifo_core_3000::sptr dma_fifo_core_3000::make(wb_iface::sptr iface, const size_t set_base, const size_t rb_addr)
+{
+    if (check(iface, set_base, rb_addr)) {
+        return sptr(new dma_fifo_core_3000_impl(iface, set_base, rb_addr));
+    } else {
+        throw uhd::runtime_error("");
+    }
+}
+
+bool dma_fifo_core_3000::check(wb_iface::sptr iface, const size_t set_base, const size_t rb_addr)
+{
+    dma_fifo_core_3000_impl::fifo_readback fifo_rb(iface, set_base, rb_addr);
+    return fifo_rb.is_fifo_instantiated();
+}
diff --git a/host/lib/usrp/cores/dma_fifo_core_3000.hpp b/host/lib/usrp/cores/dma_fifo_core_3000.hpp
new file mode 100644
index 000000000..207ee3446
--- /dev/null
+++ b/host/lib/usrp/cores/dma_fifo_core_3000.hpp
@@ -0,0 +1,76 @@
+//
+// Copyright 2015 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_LIBUHD_USRP_DMA_FIFO_CORE_3000_HPP
+#define INCLUDED_LIBUHD_USRP_DMA_FIFO_CORE_3000_HPP
+
+#include <uhd/config.hpp>
+#include <boost/shared_ptr.hpp>
+#include <boost/noncopyable.hpp>
+#include <uhd/types/wb_iface.hpp>
+
+
+class dma_fifo_core_3000 : boost::noncopyable
+{
+public:
+    typedef boost::shared_ptr<dma_fifo_core_3000> sptr;
+    virtual ~dma_fifo_core_3000(void) = 0;
+
+    /*!
+     * Create a DMA FIFO controller using the given bus, settings and readback base
+     * Throws uhd::runtime_error if a DMA FIFO is not instantiated in the FPGA
+     */
+    static sptr make(uhd::wb_iface::sptr iface, const size_t set_base, const size_t rb_addr);
+
+    /*!
+     * Check if a DMA FIFO is instantiated in the FPGA
+     */
+    static bool check(uhd::wb_iface::sptr iface, const size_t set_base, const size_t rb_addr);
+
+    /*!
+     * Get the (approx) number of elements currently in the DMA FIFO
+     */
+    virtual boost::uint32_t get_occupied_cnt() = 0;
+
+    /*!
+     * Run the built-in-self-test routine for the DMA FIFO
+     */
+    virtual boost::uint8_t run_bist(bool finite = true, boost::uint32_t timeout_ms = 500) = 0;
+
+    /*!
+     * Is extended BIST supported
+     */
+    virtual bool ext_bist_supported() = 0;
+
+    /*!
+     * Run the built-in-self-test routine for the DMA FIFO (extended BIST only)
+     */
+    virtual boost::uint8_t run_ext_bist(
+        bool finite,
+        boost::uint32_t rx_samp_delay,
+        boost::uint32_t tx_pkt_delay,
+        boost::uint32_t sid,
+        boost::uint32_t timeout_ms = 500) = 0;
+
+    /*!
+     * Get the throughput measured from the last invocation of the BIST (extended BIST only)
+     */
+    virtual double get_bist_throughput(double fifo_clock_rate) = 0;
+
+};
+
+#endif /* INCLUDED_LIBUHD_USRP_DMA_FIFO_CORE_3000_HPP */