x300: UHD is now compatible with FPGA images with Aurora support

- UHD and ZPU is now aware of Aurora SFP+ transceivers in the FPGA image
- Added script to exercise Aurora BIST features

2 files changed, 45 insertions, 25 deletions

diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 2a1e77611..2fb7df954 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -65,12 +65,25 @@ static std::string get_fpga_option(wb_iface::sptr zpu_ctrl) {
     //Possible options:
     //1G  = {0:1G, 1:1G} w/ DRAM, HG  = {0:1G, 1:10G} w/ DRAM, XG  = {0:10G, 1:10G} w/ DRAM
     //1GS = {0:1G, 1:1G} w/ SRAM, HGS = {0:1G, 1:10G} w/ SRAM, XGS = {0:10G, 1:10G} w/ SRAM
+    //HA  = {0:1G, 1:Aurora} w/ DRAM, XA  = {0:10G, 1:Aurora} w/ DRAM
 
     std::string option;
-    bool eth0XG = (zpu_ctrl->peek32(SR_ADDR(SET0_BASE, ZPU_RB_ETH_TYPE0)) == 0x1);
-    bool eth1XG = (zpu_ctrl->peek32(SR_ADDR(SET0_BASE, ZPU_RB_ETH_TYPE1)) == 0x1);
-    option = (eth0XG && eth1XG) ? "XG" : (eth1XG ? "HG" : "1G");
-
+    uint32_t sfp0_type = zpu_ctrl->peek32(SR_ADDR(SET0_BASE, ZPU_RB_SFP0_TYPE));
+    uint32_t sfp1_type = zpu_ctrl->peek32(SR_ADDR(SET0_BASE, ZPU_RB_SFP1_TYPE));
+
+    if (sfp0_type == RB_SFP_1G_ETH  and sfp1_type == RB_SFP_1G_ETH) {
+        option = "1G";
+    } else if (sfp0_type == RB_SFP_1G_ETH  and sfp1_type == RB_SFP_10G_ETH) {
+        option = "HG";
+    } else if (sfp0_type == RB_SFP_10G_ETH  and sfp1_type == RB_SFP_10G_ETH) {
+        option = "XG";
+    } else if (sfp0_type == RB_SFP_1G_ETH  and sfp1_type == RB_SFP_AURORA) {
+        option = "HA";
+    } else if (sfp0_type == RB_SFP_10G_ETH  and sfp1_type == RB_SFP_AURORA) {
+        option = "XA";
+    } else {
+        option = "HG";  //Default
+    }
     if (not has_dram_buff(zpu_ctrl)) {
         option += "S";
     }
@@ -1356,11 +1369,16 @@ x300_impl::both_xports_t x300_impl::make_transport(
                 max_link_rate += X300_MAX_RATE_10GIGE;
             }
             _tree->access<double>(mboard_path).set(max_link_rate);
-        } else if (mb.loaded_fpga_image.substr(0,2) == "XG") {
+        } else if (mb.loaded_fpga_image.substr(0,2) == "XG" or mb.loaded_fpga_image.substr(0,2) == "XA") {
             eth_data_rec_frame_size = X300_10GE_DATA_FRAME_MAX_SIZE;
             size_t max_link_rate = X300_MAX_RATE_10GIGE;
             max_link_rate *= mb.eth_conns.size();
             _tree->access<double>(mboard_path).set(max_link_rate);
+        } else if (mb.loaded_fpga_image.substr(0,2) == "HA") {
+            eth_data_rec_frame_size = X300_1GE_DATA_FRAME_MAX_SIZE;
+            size_t max_link_rate = X300_MAX_RATE_1GIGE;
+            max_link_rate *= mb.eth_conns.size();
+            _tree->access<double>(mboard_path).set(max_link_rate);
         }
 
         if (eth_data_rec_frame_size == 0) {
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index de3a3161a..69a8d5d9f 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -57,10 +57,8 @@ static const uint32_t RB32_MISC_INS        = 36;
 
 }}} // namespace
 
-#define localparam static const int
-
-localparam BL_ADDRESS    = 0;
-localparam BL_DATA       = 1;
+static const int BL_ADDRESS    = 0;
+static const int BL_DATA       = 1;
 
 //wishbone settings map - relevant to host code
 #define SET0_BASE     0xa000
@@ -70,15 +68,15 @@ localparam BL_DATA       = 1;
 #define I2C1_BASE     0xff00
 #define SR_ADDR(base, offset) ((base) + (offset)*4)
 
-localparam ZPU_SR_LEDS       = 00;
-localparam ZPU_SR_SW_RST     = 01;
-localparam ZPU_SR_CLOCK_CTRL = 02;
-localparam ZPU_SR_XB_LOCAL   = 03;
-localparam ZPU_SR_SPI        = 32;
-localparam ZPU_SR_ETHINT0    = 40;
-localparam ZPU_SR_ETHINT1    = 56;
-localparam ZPU_SR_DRAM_FIFO0 = 72;
-localparam ZPU_SR_DRAM_FIFO1 = 80;
+static const int ZPU_SR_LEDS       = 00;
+static const int ZPU_SR_SW_RST     = 01;
+static const int ZPU_SR_CLOCK_CTRL = 02;
+static const int ZPU_SR_XB_LOCAL   = 03;
+static const int ZPU_SR_SPI        = 32;
+static const int ZPU_SR_ETHINT0    = 40;
+static const int ZPU_SR_ETHINT1    = 56;
+static const int ZPU_SR_DRAM_FIFO0 = 72;
+static const int ZPU_SR_DRAM_FIFO1 = 80;
 
 //reset bits
 #define ZPU_SR_SW_RST_ETH_PHY           (1<<0)
@@ -86,13 +84,17 @@ localparam ZPU_SR_DRAM_FIFO1 = 80;
 #define ZPU_SR_SW_RST_RADIO_CLK_PLL     (1<<2)
 #define ZPU_SR_SW_RST_ADC_IDELAYCTRL    (1<<3)
 
-localparam ZPU_RB_SPI        = 2;
-localparam ZPU_RB_CLK_STATUS = 3;
-localparam ZPU_RB_COMPAT_NUM = 6;
-localparam ZPU_RB_ETH_TYPE0  = 4;
-localparam ZPU_RB_ETH_TYPE1  = 5;
-localparam ZPU_RB_DRAM_FIFO0 = 10;
-localparam ZPU_RB_DRAM_FIFO1 = 11;
+static const int ZPU_RB_SPI        = 2;
+static const int ZPU_RB_CLK_STATUS = 3;
+static const int ZPU_RB_COMPAT_NUM = 6;
+static const int ZPU_RB_SFP0_TYPE  = 4;
+static const int ZPU_RB_SFP1_TYPE  = 5;
+static const int ZPU_RB_DRAM_FIFO0 = 10;
+static const int ZPU_RB_DRAM_FIFO1 = 11;
+
+static const uint32_t RB_SFP_1G_ETH  = 0;
+static const uint32_t RB_SFP_10G_ETH = 1;
+static const uint32_t RB_SFP_AURORA  = 2;
 
 //spi slaves on radio
 #define DB_DAC_SEN      (1 << 7)