x300: support new 120 MHz bandwidth versions of the NI-branded X310s

3 files changed, 103 insertions, 85 deletions

diff --git a/host/lib/transport/nirio/rpc/rpc_client.cpp b/host/lib/transport/nirio/rpc/rpc_client.cpp
index cf8e9c1a9..48f47cfae 100644
--- a/host/lib/transport/nirio/rpc/rpc_client.cpp
+++ b/host/lib/transport/nirio/rpc/rpc_client.cpp
@@ -52,7 +52,7 @@ rpc_client::rpc_client (
         //- address_configured: Only return addresses if a non-loopback address is configured for the system.
         //- numeric_host: No name resolution should be attempted for host
         //- numeric_service: No name resolution should be attempted for service
-        tcp::resolver::query::flags query_flags;
+        tcp::resolver::query::flags query_flags = tcp::resolver::query::passive;
         tcp::resolver::query query(tcp::v4(), server, port, query_flags);
         tcp::resolver::iterator iterator = resolver.resolve(query);
 
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index c7980c997..95ac3af38 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -41,7 +41,7 @@
 
 #define NIUSRPRIO_DEFAULT_RPC_PORT "5444"
 
-#define X300_REV(x) (x - "A" + 1)
+#define X300_REV(x) ((x) - "A" + 1)
 
 using namespace uhd;
 using namespace uhd::usrp;
@@ -1722,14 +1722,20 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
                 case X300_USRP_PCIE_SSID:
                     mb_type = USRP_X300_MB; break;
                 case X310_USRP_PCIE_SSID:
-                case X310_2940R_PCIE_SSID:
-                case X310_2942R_PCIE_SSID:
-                case X310_2943R_PCIE_SSID:
-                case X310_2944R_PCIE_SSID:
-                case X310_2950R_PCIE_SSID:
-                case X310_2952R_PCIE_SSID:
-                case X310_2953R_PCIE_SSID:
-                case X310_2954R_PCIE_SSID:
+                case X310_2940R_40MHz_PCIE_SSID:
+                case X310_2940R_120MHz_PCIE_SSID:
+                case X310_2942R_40MHz_PCIE_SSID:
+                case X310_2942R_120MHz_PCIE_SSID:
+                case X310_2943R_40MHz_PCIE_SSID:
+                case X310_2943R_120MHz_PCIE_SSID:
+                case X310_2944R_40MHz_PCIE_SSID:
+                case X310_2950R_40MHz_PCIE_SSID:
+                case X310_2950R_120MHz_PCIE_SSID:
+                case X310_2952R_40MHz_PCIE_SSID:
+                case X310_2952R_120MHz_PCIE_SSID:
+                case X310_2953R_40MHz_PCIE_SSID:
+                case X310_2953R_120MHz_PCIE_SSID:
+                case X310_2954R_40MHz_PCIE_SSID:
                     mb_type = USRP_X310_MB; break;
                 default:
                     mb_type = UNKNOWN;      break;
@@ -1757,14 +1763,20 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
             case X300_USRP_PCIE_SSID:
                 mb_type = USRP_X300_MB; break;
             case X310_USRP_PCIE_SSID:
-            case X310_2940R_PCIE_SSID:
-            case X310_2942R_PCIE_SSID:
-            case X310_2943R_PCIE_SSID:
-            case X310_2944R_PCIE_SSID:
-            case X310_2950R_PCIE_SSID:
-            case X310_2952R_PCIE_SSID:
-            case X310_2953R_PCIE_SSID:
-            case X310_2954R_PCIE_SSID:
+            case X310_2940R_40MHz_PCIE_SSID:
+            case X310_2940R_120MHz_PCIE_SSID:
+            case X310_2942R_40MHz_PCIE_SSID:
+            case X310_2942R_120MHz_PCIE_SSID:
+            case X310_2943R_40MHz_PCIE_SSID:
+            case X310_2943R_120MHz_PCIE_SSID:
+            case X310_2944R_40MHz_PCIE_SSID:
+            case X310_2950R_40MHz_PCIE_SSID:
+            case X310_2950R_120MHz_PCIE_SSID:
+            case X310_2952R_40MHz_PCIE_SSID:
+            case X310_2952R_120MHz_PCIE_SSID:
+            case X310_2953R_40MHz_PCIE_SSID:
+            case X310_2953R_120MHz_PCIE_SSID:
+            case X310_2954R_40MHz_PCIE_SSID:
                 mb_type = USRP_X310_MB; break;
             default:
                 UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl;
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index f920b5ae2..68f438b7f 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -25,40 +25,40 @@
 
 #define localparam static const int
 
-localparam SR_DACSYNC   = 5;
-localparam SR_LOOPBACK  = 6;
-localparam SR_TEST      = 7;
-localparam SR_SPI       = 8;
-localparam SR_GPIO      = 16;
-localparam SR_MISC_OUTS = 24;
-localparam SR_READBACK  = 32;
-localparam SR_TX_CTRL   = 64;
-localparam SR_RX_CTRL   = 96;
-localparam SR_TIME      = 128;
-localparam SR_RX_DSP    = 144;
-localparam SR_TX_DSP    = 184;
-localparam SR_LEDS      = 195;
-localparam SR_FP_GPIO   = 200;
-localparam SR_RX_FRONT  = 208;
-localparam SR_TX_FRONT  = 216;
-
-localparam RB32_GPIO            = 0;
-localparam RB32_SPI             = 4;
-localparam RB64_TIME_NOW        = 8;
-localparam RB64_TIME_PPS        = 16;
-localparam RB32_TEST            = 24;
-localparam RB32_RX              = 28;
-localparam RB32_FP_GPIO         = 32;
-
-localparam BL_ADDRESS     = 0;
-localparam BL_DATA        = 1;
+localparam SR_DACSYNC    = 5;
+localparam SR_LOOPBACK   = 6;
+localparam SR_TEST       = 7;
+localparam SR_SPI        = 8;
+localparam SR_GPIO       = 16;
+localparam SR_MISC_OUTS  = 24;
+localparam SR_READBACK   = 32;
+localparam SR_TX_CTRL    = 64;
+localparam SR_RX_CTRL    = 96;
+localparam SR_TIME       = 128;
+localparam SR_RX_DSP     = 144;
+localparam SR_TX_DSP     = 184;
+localparam SR_LEDS       = 196;
+localparam SR_FP_GPIO    = 200;
+localparam SR_RX_FRONT   = 208;
+localparam SR_TX_FRONT   = 216;
+
+localparam RB32_GPIO     = 0;
+localparam RB32_SPI      = 4;
+localparam RB64_TIME_NOW = 8;
+localparam RB64_TIME_PPS = 16;
+localparam RB32_TEST     = 24;
+localparam RB32_RX       = 28;
+localparam RB32_FP_GPIO  = 32;
+
+localparam BL_ADDRESS    = 0;
+localparam BL_DATA       = 1;
 
 //wishbone settings map - relevant to host code
-#define SET0_BASE 0xa000
-#define SETXB_BASE 0xb000
-#define BOOT_LDR_BASE 0xFA00
-#define I2C0_BASE 0xfe00
-#define I2C1_BASE 0xff00
+#define SET0_BASE     0xa000
+#define SETXB_BASE    0xb000
+#define BOOT_LDR_BASE 0xfa00
+#define I2C0_BASE     0xfe00
+#define I2C1_BASE     0xff00
 #define SR_ADDR(base, offset) ((base) + (offset)*4)
 
 localparam ZPU_SR_LEDS       = 00;
@@ -70,56 +70,62 @@ localparam ZPU_SR_ETHINT0    = 40;
 localparam ZPU_SR_ETHINT1    = 56;
 
 //clock controls
-#define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL  0x00
-#define ZPU_SR_CLOCK_CTRL_CLK_SRC_INTERNAL  0x02
-#define ZPU_SR_CLOCK_CTRL_CLK_SRC_GPSDO     0x03
-#define ZPU_SR_CLOCK_CTRL_PPS_SRC_EXTERNAL  0x00
-#define ZPU_SR_CLOCK_CTRL_PPS_SRC_INTERNAL  0x02
-#define ZPU_SR_CLOCK_CTRL_PPS_SRC_GPSDO     0x03
-
-localparam ZPU_RB_SPI = 2;
+#define ZPU_SR_CLOCK_CTRL_CLK_SRC_EXTERNAL 0x00
+#define ZPU_SR_CLOCK_CTRL_CLK_SRC_INTERNAL 0x02
+#define ZPU_SR_CLOCK_CTRL_CLK_SRC_GPSDO    0x03
+#define ZPU_SR_CLOCK_CTRL_PPS_SRC_EXTERNAL 0x00
+#define ZPU_SR_CLOCK_CTRL_PPS_SRC_INTERNAL 0x02
+#define ZPU_SR_CLOCK_CTRL_PPS_SRC_GPSDO    0x03
+
+localparam ZPU_RB_SPI        = 2;
 localparam ZPU_RB_CLK_STATUS = 3;
 localparam ZPU_RB_COMPAT_NUM = 6;
 localparam ZPU_RB_ETH_TYPE0  = 4;
 localparam ZPU_RB_ETH_TYPE1  = 5;
 
 //clock status
-#define ZPU_RB_CLK_STATUS_LMK_STATUS    (0x3 << 0)
-#define ZPU_RB_CLK_STATUS_LMK_LOCK      (0x1 << 2)
-#define ZPU_RB_CLK_STATUS_LMK_HOLDOVER  (0x1 << 3)
-#define ZPU_RB_CLK_STATUS_PPS_DETECT    (0x1 << 4)
+#define ZPU_RB_CLK_STATUS_LMK_STATUS   (0x3 << 0)
+#define ZPU_RB_CLK_STATUS_LMK_LOCK     (0x1 << 2)
+#define ZPU_RB_CLK_STATUS_LMK_HOLDOVER (0x1 << 3)
+#define ZPU_RB_CLK_STATUS_PPS_DETECT   (0x1 << 4)
 
 //spi slaves on radio
-#define DB_DAC_SEN (1 << 7)
-#define DB_ADC_SEN (1 << 6)
+#define DB_DAC_SEN      (1 << 7)
+#define DB_ADC_SEN      (1 << 6)
 #define DB_RX_LSADC_SEN (1 << 5)
 #define DB_RX_LSDAC_SEN (1 << 4)
 #define DB_TX_LSADC_SEN (1 << 3)
 #define DB_TX_LSDAC_SEN (1 << 2)
-#define DB_RX_SEN (1 << 1)
-#define DB_TX_SEN (1 << 0)
+#define DB_RX_SEN       (1 << 1)
+#define DB_TX_SEN       (1 << 0)
 
 //-------------------------------------------------------------------
 // PCIe Registers
 //-------------------------------------------------------------------
 
-static const uint32_t X300_PCIE_VID         = 0x1093;
-static const uint32_t X300_PCIE_PID         = 0xC4C4;
-static const uint32_t X300_USRP_PCIE_SSID   = 0x7736;
-static const uint32_t X310_USRP_PCIE_SSID   = 0x76CA;
-static const uint32_t X310_2940R_PCIE_SSID  = 0x772B;
-static const uint32_t X310_2942R_PCIE_SSID  = 0x772C;
-static const uint32_t X310_2943R_PCIE_SSID  = 0x772D;
-static const uint32_t X310_2944R_PCIE_SSID  = 0x772E;
-static const uint32_t X310_2950R_PCIE_SSID  = 0x772F;
-static const uint32_t X310_2952R_PCIE_SSID  = 0x7730;
-static const uint32_t X310_2953R_PCIE_SSID  = 0x7731;
-static const uint32_t X310_2954R_PCIE_SSID  = 0x7732;
+static const uint32_t X300_PCIE_VID               = 0x1093;
+static const uint32_t X300_PCIE_PID               = 0xC4C4;
+static const uint32_t X300_USRP_PCIE_SSID         = 0x7736;
+static const uint32_t X310_USRP_PCIE_SSID         = 0x76CA;
+static const uint32_t X310_2940R_40MHz_PCIE_SSID  = 0x772B;
+static const uint32_t X310_2940R_120MHz_PCIE_SSID = 0x77FB;
+static const uint32_t X310_2942R_40MHz_PCIE_SSID  = 0x772C;
+static const uint32_t X310_2942R_120MHz_PCIE_SSID = 0x77FC;
+static const uint32_t X310_2943R_40MHz_PCIE_SSID  = 0x772D;
+static const uint32_t X310_2943R_120MHz_PCIE_SSID = 0x77FD;
+static const uint32_t X310_2944R_40MHz_PCIE_SSID  = 0x772E;
+static const uint32_t X310_2950R_40MHz_PCIE_SSID  = 0x772F;
+static const uint32_t X310_2950R_120MHz_PCIE_SSID = 0x77FE;
+static const uint32_t X310_2952R_40MHz_PCIE_SSID  = 0x7730;
+static const uint32_t X310_2952R_120MHz_PCIE_SSID = 0x77FF;
+static const uint32_t X310_2953R_40MHz_PCIE_SSID  = 0x7731;
+static const uint32_t X310_2953R_120MHz_PCIE_SSID = 0x7800;
+static const uint32_t X310_2954R_40MHz_PCIE_SSID  = 0x7732;
 
 static const uint32_t FPGA_X3xx_SIG_VALUE   = 0x58333030;
 
 static const uint32_t PCIE_FPGA_ADDR_BASE   = 0xC0000;
-#define PCIE_FPGA_REG(X)                    (PCIE_FPGA_ADDR_BASE + X)
+#define PCIE_FPGA_REG(X)                    (PCIE_FPGA_ADDR_BASE + (X))
 
 static const uint32_t FPGA_PCIE_SIG_REG     = PCIE_FPGA_REG(0x0000);
 static const uint32_t FPGA_CNTR_LO_REG      = PCIE_FPGA_REG(0x0004);
@@ -140,8 +146,8 @@ static const uint32_t DMA_FRAME_SIZE_REG    = 0x4;
 static const uint32_t DMA_SAMPLE_COUNT_REG  = 0x8;
 static const uint32_t DMA_PKT_COUNT_REG     = 0xC;
 
-#define PCIE_TX_DMA_REG(REG, CHAN)          (PCIE_TX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG)
-#define PCIE_RX_DMA_REG(REG, CHAN)          (PCIE_RX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG)
+#define PCIE_TX_DMA_REG(REG, CHAN)          (PCIE_TX_DMA_REG_BASE + ((CHAN)*DMA_REG_GRP_SIZE) + (REG))
+#define PCIE_RX_DMA_REG(REG, CHAN)          (PCIE_RX_DMA_REG_BASE + ((CHAN)*DMA_REG_GRP_SIZE) + (REG))
 
 static const uint32_t DMA_CTRL_DISABLED     = 0x00000000;
 static const uint32_t DMA_CTRL_ENABLED      = 0x00000002;
@@ -154,15 +160,15 @@ static const uint32_t DMA_STATUS_ERROR      = 0x00000001;
 static const uint32_t DMA_STATUS_BUSY       = 0x00000002;
 
 static const uint32_t PCIE_ROUTER_REG_BASE  = PCIE_FPGA_REG(0x0500);
-#define PCIE_ROUTER_REG(X)                  (PCIE_ROUTER_REG_BASE + X)
+#define PCIE_ROUTER_REG(X)                  (PCIE_ROUTER_REG_BASE + (X))
 
 static const uint32_t PCIE_ZPU_DATA_BASE    = 0x30000;
 static const uint32_t PCIE_ZPU_READ_BASE    = 0x20000;  //Trig and Status share the same base
 static const uint32_t PCIE_ZPU_STATUS_BASE  = 0x20000;
 
-#define PCIE_ZPU_DATA_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_DATA_BASE) + X)
-#define PCIE_ZPU_READ_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_READ_BASE) + X)
-#define PCIE_ZPU_STATUS_REG(X)              (PCIE_FPGA_REG(PCIE_ZPU_STATUS_BASE) + X)
+#define PCIE_ZPU_DATA_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_DATA_BASE) + (X))
+#define PCIE_ZPU_READ_REG(X)                (PCIE_FPGA_REG(PCIE_ZPU_READ_BASE) + (X))
+#define PCIE_ZPU_STATUS_REG(X)              (PCIE_FPGA_REG(PCIE_ZPU_STATUS_BASE) + (X))
 
 static const uint32_t PCIE_ZPU_READ_START       = 0x0;
 static const uint32_t PCIE_ZPU_READ_CLOBBER     = 0x80000000;