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| author | Jonathon Pendlum <jonathon.pendlum@ettus.com> | 2015-04-24 15:53:43 -0700 |
|---|---|---|
| committer | Jonathon Pendlum <jonathon.pendlum@ettus.com> | 2015-04-24 15:53:43 -0700 |
| commit | 64990acea741768becafb3e9dee171274f23f9d9 (patch) | |
| tree | 7095a7b9eda8ec3c293d4b99173a6bd11eeb877f /host/lib | |
| parent | 16ef969d87cf74448d44dc1f31a5870cda4a8446 (diff) | |
| download | uhd-64990acea741768becafb3e9dee171274f23f9d9.tar.gz uhd-64990acea741768becafb3e9dee171274f23f9d9.tar.bz2 uhd-64990acea741768becafb3e9dee171274f23f9d9.zip | |
e300: Reduced AD9361's RX data delay to improve timing in FPGA capture interface
Diffstat (limited to 'host/lib')
| -rw-r--r-- | host/lib/usrp/e300/e300_defaults.hpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/e300/e300_defaults.hpp b/host/lib/usrp/e300/e300_defaults.hpp index 8fe8c3a05..537a0cf3e 100644 --- a/host/lib/usrp/e300/e300_defaults.hpp +++ b/host/lib/usrp/e300/e300_defaults.hpp @@ -70,7 +70,7 @@ public: digital_interface_delays_t get_digital_interface_timing() { digital_interface_delays_t delays; delays.rx_clk_delay = 0; - delays.rx_data_delay = 0xF; + delays.rx_data_delay = 0x8; delays.tx_clk_delay = 0; delays.tx_data_delay = 0xF; return delays; |