x300: Added new Rev7+ X3x0 MB product codes

- Added new PCIe and MB PIDs for new boards
- Added an error if MB PID is invalid

2 files changed, 54 insertions, 2 deletions

diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 8c565a252..34090faa3 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -399,7 +399,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
             default:
                 nirio_status_to_exception(status, "Motherboard detection error. Please ensure that you \
                     have a valid USRP X3x0, NI USRP-294xR or NI USRP-295xR device and that all the device \
-                    driver have been loaded.");
+                    drivers have loaded successfully.");
         }
         //Load the lvbitx onto the device
         UHD_MSG(status) << boost::format("Using LVBITX bitfile %s...\n") % lvbitx->get_bitfile_path();
@@ -570,7 +570,9 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
             product_name = "X310";
             break;
         default:
-            break;
+            throw uhd::runtime_error("Unrecognized product type. \n"
+                                     "Either the software does not support this device or it is too old for the hardware.\n"
+                                     "Please update your UHD/NI-USRP version and retry.");
     }
     _tree->create<std::string>(mb_path / "name").set(product_name);
     _tree->create<std::string>(mb_path / "codename").set("Yetti");
@@ -1744,6 +1746,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
             //The PCIe ID -> MB mapping may be different from the EEPROM -> MB mapping
             switch (pid) {
                 case X300_USRP_PCIE_SSID:
+                case X300_USRP_PCIE_R7_SSID:
                     mb_type = USRP_X300_MB; break;
                 case X310_USRP_PCIE_SSID:
                 case X310_2940R_40MHz_PCIE_SSID:
@@ -1760,6 +1763,21 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
                 case X310_2953R_40MHz_PCIE_SSID:
                 case X310_2953R_120MHz_PCIE_SSID:
                 case X310_2954R_40MHz_PCIE_SSID:
+                case X310_USRP_PCIE_R7_SSID:
+                case X310_2940R_40MHz_PCIE_R7_SSID:
+                case X310_2940R_120MHz_PCIE_R7_SSID:
+                case X310_2942R_40MHz_PCIE_R7_SSID:
+                case X310_2942R_120MHz_PCIE_R7_SSID:
+                case X310_2943R_40MHz_PCIE_R7_SSID:
+                case X310_2943R_120MHz_PCIE_R7_SSID:
+                case X310_2944R_40MHz_PCIE_R7_SSID:
+                case X310_2950R_40MHz_PCIE_R7_SSID:
+                case X310_2950R_120MHz_PCIE_R7_SSID:
+                case X310_2952R_40MHz_PCIE_R7_SSID:
+                case X310_2952R_120MHz_PCIE_R7_SSID:
+                case X310_2953R_40MHz_PCIE_R7_SSID:
+                case X310_2953R_120MHz_PCIE_R7_SSID:
+                case X310_2954R_40MHz_PCIE_R7_SSID:
                     mb_type = USRP_X310_MB; break;
                 default:
                     mb_type = UNKNOWN;      break;
@@ -1785,6 +1803,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
         switch (product_num) {
             //The PCIe ID -> MB mapping may be different from the EEPROM -> MB mapping
             case X300_USRP_PCIE_SSID:
+            case X300_USRP_PCIE_R7_SSID:
                 mb_type = USRP_X300_MB; break;
             case X310_USRP_PCIE_SSID:
             case X310_2940R_40MHz_PCIE_SSID:
@@ -1801,6 +1820,21 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
             case X310_2953R_40MHz_PCIE_SSID:
             case X310_2953R_120MHz_PCIE_SSID:
             case X310_2954R_40MHz_PCIE_SSID:
+            case X310_USRP_PCIE_R7_SSID:
+            case X310_2940R_40MHz_PCIE_R7_SSID:
+            case X310_2940R_120MHz_PCIE_R7_SSID:
+            case X310_2942R_40MHz_PCIE_R7_SSID:
+            case X310_2942R_120MHz_PCIE_R7_SSID:
+            case X310_2943R_40MHz_PCIE_R7_SSID:
+            case X310_2943R_120MHz_PCIE_R7_SSID:
+            case X310_2944R_40MHz_PCIE_R7_SSID:
+            case X310_2950R_40MHz_PCIE_R7_SSID:
+            case X310_2950R_120MHz_PCIE_R7_SSID:
+            case X310_2952R_40MHz_PCIE_R7_SSID:
+            case X310_2952R_120MHz_PCIE_R7_SSID:
+            case X310_2953R_40MHz_PCIE_R7_SSID:
+            case X310_2953R_120MHz_PCIE_R7_SSID:
+            case X310_2954R_40MHz_PCIE_R7_SSID:
                 mb_type = USRP_X310_MB; break;
             default:
                 UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl;
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index e984eb908..d5dc8140c 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -106,6 +106,7 @@ localparam ZPU_RB_ETH_TYPE1  = 5;
 
 static const uint32_t X300_PCIE_VID               = 0x1093;
 static const uint32_t X300_PCIE_PID               = 0xC4C4;
+//Rev 0-6 motherboard/PCIe IDs
 static const uint32_t X300_USRP_PCIE_SSID         = 0x7736;
 static const uint32_t X310_USRP_PCIE_SSID         = 0x76CA;
 static const uint32_t X310_2940R_40MHz_PCIE_SSID  = 0x772B;
@@ -122,6 +123,23 @@ static const uint32_t X310_2952R_120MHz_PCIE_SSID = 0x77FF;
 static const uint32_t X310_2953R_40MHz_PCIE_SSID  = 0x7731;
 static const uint32_t X310_2953R_120MHz_PCIE_SSID = 0x7800;
 static const uint32_t X310_2954R_40MHz_PCIE_SSID  = 0x7732;
+//Rev 7+ motherboard/PCIe IDs
+static const uint32_t X300_USRP_PCIE_R7_SSID         = 0x7861;
+static const uint32_t X310_USRP_PCIE_R7_SSID         = 0x7862;
+static const uint32_t X310_2940R_40MHz_PCIE_R7_SSID  = 0x7853;
+static const uint32_t X310_2940R_120MHz_PCIE_R7_SSID = 0x785B;
+static const uint32_t X310_2942R_40MHz_PCIE_R7_SSID  = 0x7854;
+static const uint32_t X310_2942R_120MHz_PCIE_R7_SSID = 0x785C;
+static const uint32_t X310_2943R_40MHz_PCIE_R7_SSID  = 0x7855;
+static const uint32_t X310_2943R_120MHz_PCIE_R7_SSID = 0x785D;
+static const uint32_t X310_2944R_40MHz_PCIE_R7_SSID  = 0x7856;
+static const uint32_t X310_2950R_40MHz_PCIE_R7_SSID  = 0x7857;
+static const uint32_t X310_2950R_120MHz_PCIE_R7_SSID = 0x785E;
+static const uint32_t X310_2952R_40MHz_PCIE_R7_SSID  = 0x7858;
+static const uint32_t X310_2952R_120MHz_PCIE_R7_SSID = 0x785F;
+static const uint32_t X310_2953R_40MHz_PCIE_R7_SSID  = 0x7859;
+static const uint32_t X310_2953R_120MHz_PCIE_R7_SSID = 0x7860;
+static const uint32_t X310_2954R_40MHz_PCIE_R7_SSID  = 0x785A;
 
 static const uint32_t FPGA_X3xx_SIG_VALUE   = 0x58333030;