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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-22 17:57:45 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-22 17:57:45 -0700 |
| commit | 1dad62c7801d337db79e7a01310c04ef68a83483 (patch) | |
| tree | d292ce3aef2dcc38583c31d3f08dbe627296b25f /host/lib | |
| parent | f76f599be281d773736940d53aafc6d7e9d536ca (diff) | |
| download | uhd-1dad62c7801d337db79e7a01310c04ef68a83483.tar.gz uhd-1dad62c7801d337db79e7a01310c04ef68a83483.tar.bz2 uhd-1dad62c7801d337db79e7a01310c04ef68a83483.zip | |
x300: Updated CLK->DATA delay for ADC
- The value was originally empirically determined based on self-cal
results. After the fix for uncalibrated IDELAY, the self-cal offset
data was no longer correct.
- The new delay through the ADC ensures that the self-cal nominally
pick the halfway tap of 16
Diffstat (limited to 'host/lib')
| -rw-r--r-- | host/lib/usrp/x300/x300_adc_ctrl.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/x300/x300_adc_ctrl.cpp b/host/lib/usrp/x300/x300_adc_ctrl.cpp index edb4ce885..ce6102b35 100644 --- a/host/lib/usrp/x300/x300_adc_ctrl.cpp +++ b/host/lib/usrp/x300/x300_adc_ctrl.cpp @@ -55,8 +55,8 @@ public: _ads62p48_regs.lvds_cmos = ads62p48_regs_t::LVDS_CMOS_DDR_LVDS; _ads62p48_regs.channel_control = ads62p48_regs_t::CHANNEL_CONTROL_INDEPENDENT; _ads62p48_regs.data_format = ads62p48_regs_t::DATA_FORMAT_2S_COMPLIMENT; - _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_NORMAL; - _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_NORMAL; + _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS4_26; + _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS4_26; this->send_ads62p48_reg(0); |