usrp2: host and fw implementation for fifo control

6 files changed, 173 insertions, 3 deletions

diff --git a/host/lib/usrp/usrp2/CMakeLists.txt b/host/lib/usrp/usrp2/CMakeLists.txt
index 10f7407b0..da39d9df1 100644
--- a/host/lib/usrp/usrp2/CMakeLists.txt
+++ b/host/lib/usrp/usrp2/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2011 Ettus Research LLC
+# Copyright 2011-2012 Ettus Research LLC
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -32,5 +32,6 @@ IF(ENABLE_USRP2)
         ${CMAKE_CURRENT_SOURCE_DIR}/io_impl.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_iface.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_impl.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/usrp2_fifo_ctrl.cpp
     )
 ENDIF(ENABLE_USRP2)
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 2add74c47..2dfc7f519 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2010-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -51,6 +51,7 @@ typedef struct{
 #define USRP2_UDP_RX_DSP0_PORT 49156
 #define USRP2_UDP_TX_DSP0_PORT 49157
 #define USRP2_UDP_RX_DSP1_PORT 49158
+#define USRP2_UDP_FIFO_CRTL_PORT 49159
 #define USRP2_UDP_UART_BASE_PORT 49170
 #define USRP2_UDP_UART_GPS_PORT 49172
 
diff --git a/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp
new file mode 100644
index 000000000..0fe8898da
--- /dev/null
+++ b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp
@@ -0,0 +1,119 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include <uhd/exception.hpp>
+#include "usrp2_fifo_ctrl.hpp"
+#include <boost/thread/mutex.hpp>
+#include <boost/asio.hpp> //htonl
+
+using namespace uhd::transport;
+
+static const size_t POKE32_CMD = (1 << 8);
+static const size_t PEEK32_CMD = 0;
+static const double ACK_TIMEOUT = 0.5;
+
+class usrp2_fifo_ctrl_impl : public usrp2_fifo_ctrl{
+public:
+
+    usrp2_fifo_ctrl_impl(zero_copy_if::sptr xport):
+        _xport(xport),
+        _seq(0)
+    {
+        //NOP
+    }
+
+    void poke32(wb_addr_type addr, boost::uint32_t data){
+        boost::mutex::scoped_lock lock(_mutex);
+
+        while (_xport->get_recv_buff(0.0)){} //flush
+
+        {
+            managed_send_buffer::sptr buff = _xport->get_send_buff(0.0);
+            if (not buff){
+                throw uhd::runtime_error("poke32 in fifo ctrl timed out getting a send buffer");
+            }
+            boost::uint32_t *pkt = buff->cast<boost::uint32_t *>();
+            const boost::uint32_t ctrl_word = (addr >> 2) | POKE32_CMD | (++_seq << 16);
+            //TODO vita packer goes here, below is the payload
+            pkt[0] = htonl(ctrl_word);
+            //FIXME cant be zero, need real VRT header here, see pkt dispatcher in fpga code
+            if ((data & 0xffff) == 0) data = 1;
+            pkt[1] = htonl(data);
+            buff->commit(sizeof(boost::uint32_t)*2);
+        }
+
+        {
+            managed_recv_buffer::sptr buff = _xport->get_recv_buff(ACK_TIMEOUT);
+            if (not buff){
+                throw uhd::runtime_error("poke32 in fifo ctrl timed out getting a recv buffer");
+            }
+            const boost::uint32_t *pkt = buff->cast<const boost::uint32_t *>();
+            if (buff->size() < (sizeof(boost::uint32_t)*6) or (ntohl(pkt[4]) >> 16) != (_seq & 0xffff)){
+                throw uhd::runtime_error("poke32 in fifo ctrl got invalid ack packet");
+            }
+        }
+    }
+
+    boost::uint32_t peek32(wb_addr_type addr){
+        boost::mutex::scoped_lock lock(_mutex);
+
+        while (_xport->get_recv_buff(0.0)){} //flush
+
+        {
+            managed_send_buffer::sptr buff = _xport->get_send_buff(0.0);
+            if (not buff){
+                throw uhd::runtime_error("peek32 in fifo ctrl timed out getting a send buffer");
+            }
+            boost::uint32_t *pkt = buff->cast<boost::uint32_t *>();
+            const boost::uint32_t ctrl_word = (addr >> 2) | PEEK32_CMD | (++_seq << 16);
+            //TODO vita packer goes here, below is the payload
+            pkt[0] = htonl(ctrl_word);
+            pkt[1] = htonl(0xffffffff); //FIXME cant be zero, need real VRT header here, see pkt dispatcher in fpga code
+            buff->commit(sizeof(boost::uint32_t)*2);
+        }
+
+        {
+            managed_recv_buffer::sptr buff = _xport->get_recv_buff(ACK_TIMEOUT);
+            if (not buff){
+                throw uhd::runtime_error("peek32 in fifo ctrl timed out getting a recv buffer");
+            }
+            const boost::uint32_t *pkt = buff->cast<const boost::uint32_t *>();
+            if (buff->size() < (sizeof(boost::uint32_t)*6) or (ntohl(pkt[4]) >> 16) != (_seq & 0xffff)){
+                throw uhd::runtime_error("peek32 in fifo ctrl got invalid ack packet");
+            }
+            return ntohl(pkt[5]);
+        }
+    }
+
+    void poke16(wb_addr_type, boost::uint16_t){
+        throw uhd::not_implemented_error("poke16 not implemented in fifo ctrl module");
+    }
+
+    boost::uint16_t peek16(wb_addr_type){
+        throw uhd::not_implemented_error("peek16 not implemented in fifo ctrl module");
+    }
+
+private:
+    zero_copy_if::sptr _xport;
+    boost::mutex _mutex;
+    boost::uint32_t _seq;
+};
+
+
+usrp2_fifo_ctrl::sptr usrp2_fifo_ctrl::make(zero_copy_if::sptr xport){
+    return sptr(new usrp2_fifo_ctrl_impl(xport));
+}
diff --git a/host/lib/usrp/usrp2/usrp2_fifo_ctrl.hpp b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.hpp
new file mode 100644
index 000000000..8cdfb11a2
--- /dev/null
+++ b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.hpp
@@ -0,0 +1,39 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_USRP2_FIFO_CTRL_HPP
+#define INCLUDED_USRP2_FIFO_CTRL_HPP
+
+#include <uhd/transport/zero_copy.hpp>
+#include <boost/shared_ptr.hpp>
+#include <boost/utility.hpp>
+#include "wb_iface.hpp"
+#include <string>
+
+/*!
+ * The usrp2 FIFO control class:
+ * Provide high-speed peek/poke interface.
+ */
+class usrp2_fifo_ctrl : public wb_iface{
+public:
+    typedef boost::shared_ptr<usrp2_fifo_ctrl> sptr;
+
+    //! Make a new FIFO control object
+    static sptr make(uhd::transport::zero_copy_if::sptr xport);
+};
+
+#endif /* INCLUDED_USRP2_FIFO_CTRL_HPP */
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index 20a74db2c..5e873f741 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -377,8 +377,15 @@ usrp2_impl::usrp2_impl(const device_addr_t &_device_addr){
         _mbc[mb].tx_dsp_xport = make_xport(
             addr, BOOST_STRINGIZE(USRP2_UDP_TX_DSP0_PORT), device_args_i, "send"
         );
+        UHD_LOG << "Making transport for Control..." << std::endl;
+        _mbc[mb].fifo_ctrl_xport = make_xport(
+            addr, BOOST_STRINGIZE(USRP2_UDP_FIFO_CRTL_PORT), device_addr_t(), ""
+        );
         //set the filter on the router to take dsp data from this port
-        _mbc[mb].iface->poke32(U2_REG_ROUTER_CTRL_PORTS, USRP2_UDP_TX_DSP0_PORT);
+        _mbc[mb].iface->poke32(U2_REG_ROUTER_CTRL_PORTS, (USRP2_UDP_FIFO_CRTL_PORT << 16) | USRP2_UDP_TX_DSP0_PORT);
+
+        //create the fifo control interface for high speed register access
+        _mbc[mb].fifo_ctrl = usrp2_fifo_ctrl::make(_mbc[mb].fifo_ctrl_xport);
 
         ////////////////////////////////////////////////////////////////
         // setup the mboard eeprom
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index 6053c3890..291208eff 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -19,6 +19,7 @@
 #define INCLUDED_USRP2_IMPL_HPP
 
 #include "usrp2_iface.hpp"
+#include "usrp2_fifo_ctrl.hpp"
 #include "clock_ctrl.hpp"
 #include "codec_ctrl.hpp"
 #include "rx_frontend_core_200.hpp"
@@ -82,6 +83,7 @@ private:
     uhd::property_tree::sptr _tree;
     struct mb_container_type{
         usrp2_iface::sptr iface;
+        usrp2_fifo_ctrl::sptr fifo_ctrl;
         usrp2_clock_ctrl::sptr clock;
         usrp2_codec_ctrl::sptr codec;
         uhd::gps_ctrl::sptr gps;
@@ -95,6 +97,7 @@ private:
         user_settings_core_200::sptr user;
         std::vector<uhd::transport::zero_copy_if::sptr> rx_dsp_xports;
         uhd::transport::zero_copy_if::sptr tx_dsp_xport;
+        uhd::transport::zero_copy_if::sptr fifo_ctrl_xport;
         uhd::usrp::dboard_manager::sptr dboard_manager;
         uhd::usrp::dboard_iface::sptr dboard_iface;
         size_t rx_chan_occ, tx_chan_occ;