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| author | Josh Blum <josh@joshknows.com> | 2010-04-13 16:08:14 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-04-13 16:08:14 -0700 |
| commit | 841400bb4e72375b439f04f0bd855e64b9f83f00 (patch) | |
| tree | b92e420c42539df522153f8d8f2b6a41b6ebd7af /host/lib | |
| parent | 75dd8f674004d015425f194f8f4714b08f9ec018 (diff) | |
| download | uhd-841400bb4e72375b439f04f0bd855e64b9f83f00.tar.gz uhd-841400bb4e72375b439f04f0bd855e64b9f83f00.tar.bz2 uhd-841400bb4e72375b439f04f0bd855e64b9f83f00.zip | |
Moved ad9777 control 100% on to the host
Diffstat (limited to 'host/lib')
| -rw-r--r-- | host/lib/ic_reg_maps/gen_ad9777_regs.py | 8 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/mboard_impl.cpp | 25 |
2 files changed, 29 insertions, 4 deletions
diff --git a/host/lib/ic_reg_maps/gen_ad9777_regs.py b/host/lib/ic_reg_maps/gen_ad9777_regs.py index 5bfd404c2..135d5c724 100644 --- a/host/lib/ic_reg_maps/gen_ad9777_regs.py +++ b/host/lib/ic_reg_maps/gen_ad9777_regs.py @@ -49,7 +49,7 @@ pll_lock_indicator 0[1] 0 filter_interp_rate 1[6:7] 0 1x, 2x, 4x, 8x modulation_mode 1[4:5] 0 none, fs_2, fs_4, fs_8 zero_stuff_mode 1[3] 0 -real_mix_mode 1[2] 0 +mix_mode 1[2] 1 complex, real modulation_form 1[1] 0 e_minus_jwt, e_plus_jwt data_clk_pll_lock_sel 1[0] 0 pll_lock, data_clk ######################################################################## @@ -70,7 +70,7 @@ pll_divide_ratio 3[0:1] 0 div1, div2, div4, div8 ######################################################################## ## address 4 ######################################################################## -pll_off 4[7] 0 off, on +pll_state 4[7] 0 off, on auto_cp_control 4[6] 0 dis, enb pll_cp_control 4[0:2] 0 50ua=0, 100ua=1, 200ua=2, 400ua=3, 800ua=7 ######################################################################## @@ -81,8 +81,8 @@ qdac_fine_gain_adjust 9[0:7] 0 ######################################################################## ## address 6 and A ######################################################################## -idac_fine_coarse_adjust 6[0:3] 0 -qdac_fine_coarse_adjust A[0:3] 0 +idac_coarse_gain_adjust 6[0:3] 0 +qdac_coarse_gain_adjust A[0:3] 0 ######################################################################## ## address 7, 8 and B, C ######################################################################## diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 4361e45cd..ea268651a 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -17,6 +17,7 @@ #include "usrp2_impl.hpp" #include "usrp2_regs.hpp" +#include "ad9777_regs.hpp" #include <uhd/usrp/mboard_props.hpp> #include <uhd/utils/assert.hpp> #include <uhd/types/mac_addr.hpp> @@ -35,6 +36,30 @@ void usrp2_impl::mboard_init(void){ ); _clock_control = clock_control::make_ad9510(this); + + //setup the ad9777 dac + ad9777_regs_t ad9777_regs; + ad9777_regs.x_1r_2r_mode = ad9777_regs_t::X_1R_2R_MODE_1R; + ad9777_regs.filter_interp_rate = ad9777_regs_t::FILTER_INTERP_RATE_4X; + ad9777_regs.mix_mode = ad9777_regs_t::MIX_MODE_REAL; + ad9777_regs.pll_divide_ratio = ad9777_regs_t::PLL_DIVIDE_RATIO_DIV1; + ad9777_regs.pll_state = ad9777_regs_t::PLL_STATE_OFF; + ad9777_regs.auto_cp_control = ad9777_regs_t::AUTO_CP_CONTROL_ENB; + //I dac values + ad9777_regs.idac_fine_gain_adjust = 0; + ad9777_regs.idac_coarse_gain_adjust = 0xf; + ad9777_regs.idac_offset_adjust_lsb = 0; + ad9777_regs.idac_offset_adjust_msb = 0; + //Q dac values + ad9777_regs.qdac_fine_gain_adjust = 0; + ad9777_regs.qdac_coarse_gain_adjust = 0xf; + ad9777_regs.qdac_offset_adjust_lsb = 0; + ad9777_regs.qdac_offset_adjust_msb = 0; + //write all regs + for(boost::uint8_t addr = 0; addr <= 0xC; addr++){ + boost::uint16_t data = ad9777_regs.get_write_reg(addr); + this->transact_spi(SPI_SS_AD9777, spi_config_t::EDGE_RISE, data, 16, false /*no rb*/); + } } clock_control::sptr usrp2_impl::get_clock_control(void){ |