usrp2: added registers and handling for tx async reports

3 files changed, 20 insertions, 2 deletions

diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index 430f28390..e4a49184e 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -95,6 +95,12 @@ void usrp2_impl::io_impl::recv_pirate_loop(
             if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t);
             vrt::if_hdr_unpack_be(buff->cast<const boost::uint32_t *>(), if_packet_info);
 
+            //handle a tx async report message (TODO forward info)
+            if (if_packet_info.sid == 1 and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){
+                std::cerr << "U";
+                continue;
+            }
+
             //handle the packet count / sequence number
             if (if_packet_info.packet_count != next_packet_seq){
                 //std::cerr << "S" << (if_packet_info.packet_count - next_packet_seq)%16;
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 7518d3114..b3b03c11c 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -67,7 +67,7 @@ usrp2_mboard_impl::usrp2_mboard_impl(
         _allowed_decim_and_interp_rates.push_back(i);
     }
 
-    //setup the vrt rx registers
+    //init the rx control registers
     _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _io_helper.get_max_recv_samps_per_packet());
     _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1);
     _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset
@@ -81,6 +81,11 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     _iface->poke32(U2_REG_RX_CTRL_VRT_TRAILER, 0);
     _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq()));
 
+    //init the tx control registers
+    _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
+    _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset
+    _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1);  //sid 1 (different from rx)
+
     //init the ddc
     init_ddc_config();
 
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 1a5864c85..aa8bd860f 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -226,7 +226,7 @@
 #define U2_REG_ATR_FULL_RXSIDE  U2_REG_ATR_BASE + 14
 
 ///////////////////////////////////////////////////
-// VITA RX CTRL regs
+// RX CTRL regs
 ///////////////////////////////////////////////////
 // The following 3 are logically a single command register.
 // They are clocked into the underlying fifo when time_ticks is written.
@@ -241,4 +241,11 @@
 #define U2_REG_RX_CTRL_NSAMPS_PER_PKT    _SR_ADDR(SR_RX_CTRL + 7)
 #define U2_REG_RX_CTRL_NCHANNELS         _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources
 
+///////////////////////////////////////////////////
+// TX CTRL regs
+///////////////////////////////////////////////////
+#define U2_REG_TX_CTRL_NUM_CHAN          _SR_ADDR(SR_TX_CTRL + 0)
+#define U2_REG_TX_CTRL_CLEAR_STATE       _SR_ADDR(SR_TX_CTRL + 1)
+#define U2_REG_TX_CTRL_REPORT_SID        _SR_ADDR(SR_TX_CTRL + 2)
+
 #endif /* INCLUDED_USRP2_REGS_HPP */