fifo ctrl: various tweaks

3 files changed, 9 insertions, 10 deletions

diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 2dfc7f519..acd5d1f3a 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -30,8 +30,8 @@ extern "C" {
 #endif
 
 //fpga and firmware compatibility numbers
-#define USRP2_FPGA_COMPAT_NUM 9
-#define USRP2_FW_COMPAT_NUM 11
+#define USRP2_FPGA_COMPAT_NUM 10
+#define USRP2_FW_COMPAT_NUM 12
 #define USRP2_FW_VER_MINOR 2
 
 //used to differentiate control packets over data port
diff --git a/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp
index 090bae759..d6e68c636 100644
--- a/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_fifo_ctrl.cpp
@@ -22,6 +22,7 @@
 #include <uhd/transport/vrt_if_packet.hpp>
 #include "usrp2_fifo_ctrl.hpp"
 #include <boost/thread/mutex.hpp>
+#include <boost/thread/thread.hpp>
 #include <boost/asio.hpp> //htonl
 #include <boost/format.hpp>
 
@@ -38,7 +39,6 @@ static const boost::uint32_t MAX_SEQS_OUT = 64;
 #define SPI_CTRL SR_SPI_CORE + 1
 #define SPI_DATA SR_SPI_CORE + 2
 #define SPI_READBACK 0
-#define SPI_PERIF_MASK (1 << 10)
 // spi clock rate = master_clock/(div+1)/2 (10MHz in this case)
 #define SPI_DIVIDER 4
 
@@ -146,7 +146,7 @@ public:
     void init_spi(void){
         boost::mutex::scoped_lock lock(_mutex);
 
-        this->send_pkt(SPI_DIV, SPI_DIVIDER, POKE32_CMD | SPI_PERIF_MASK);
+        this->send_pkt(SPI_DIV, SPI_DIVIDER, POKE32_CMD);
         this->wait_for_ack(boost::int16_t(_seq-MAX_SEQS_OUT));
 
         _ctrl_word_cache = 0; // force update first time around
@@ -165,26 +165,26 @@ public:
         boost::uint32_t ctrl_word = 0;
         ctrl_word |= ((which_slave & 0xffffff) << 0);
         ctrl_word |= ((num_bits & 0x3ff) << 24);
-        if (config.mosi_edge == spi_config_t::EDGE_RISE) ctrl_word |= (1 << 31);
-        if (config.miso_edge == spi_config_t::EDGE_FALL) ctrl_word |= (1 << 30);
+        if (config.mosi_edge == spi_config_t::EDGE_FALL) ctrl_word |= (1 << 31);
+        if (config.miso_edge == spi_config_t::EDGE_RISE) ctrl_word |= (1 << 30);
 
         //load data word (must be in upper bits)
         const boost::uint32_t data_out = data << (32 - num_bits);
 
         //conditionally send control word
         if (_ctrl_word_cache != ctrl_word){
-            this->send_pkt(SPI_CTRL, ctrl_word, POKE32_CMD | SPI_PERIF_MASK);
+            this->send_pkt(SPI_CTRL, ctrl_word, POKE32_CMD);
             this->wait_for_ack(boost::int16_t(_seq-MAX_SEQS_OUT));
             _ctrl_word_cache = ctrl_word;
         }
 
         //send data word
-        this->send_pkt(SPI_DATA, data_out, POKE32_CMD | SPI_PERIF_MASK);
+        this->send_pkt(SPI_DATA, data_out, POKE32_CMD);
         this->wait_for_ack(boost::int16_t(_seq-MAX_SEQS_OUT));
 
         //conditional readback
         if (readback){
-            this->send_pkt(SPI_READBACK, 0, PEEK32_CMD | SPI_PERIF_MASK);
+            this->send_pkt(SPI_READBACK, 0, PEEK32_CMD);
             return this->wait_for_ack(boost::int16_t(_seq));
         }
 
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index 68a8c1c5f..cbe64635b 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -560,7 +560,6 @@ usrp2_impl::usrp2_impl(const device_addr_t &_device_addr){
         _mbc[mb].time64 = time64_core_200::make(
             _mbc[mb].fifo_ctrl, U2_REG_SR_ADDR(SR_TIME64), time64_rb_bases, mimo_clock_sync_delay_cycles
         );
-        //_mbc[mb].fifo_ctrl->poke32(0x7, 0x1234);
         _tree->access<double>(mb_path / "tick_rate")
             .subscribe(boost::bind(&time64_core_200::set_tick_rate, _mbc[mb].time64, _1));
         _tree->create<time_spec_t>(mb_path / "time/now")