b100: support for dual dsp

20 files changed, 332 insertions, 231 deletions

diff --git a/host/lib/usrp/b100/CMakeLists.txt b/host/lib/usrp/b100/CMakeLists.txt
index e1618a49c..28429c186 100644
--- a/host/lib/usrp/b100/CMakeLists.txt
+++ b/host/lib/usrp/b100/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2010-2011 Ettus Research LLC
+# Copyright 2011 Ettus Research LLC
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/b100_ctrl.cpp b/host/lib/usrp/b100/b100_ctrl.cpp
index 4d4520e1e..2e5afcae3 100644
--- a/host/lib/usrp/b100/b100_ctrl.cpp
+++ b/host/lib/usrp/b100/b100_ctrl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/b100_ctrl.hpp b/host/lib/usrp/b100/b100_ctrl.hpp
index ae706dbb4..17887181d 100644
--- a/host/lib/usrp/b100/b100_ctrl.hpp
+++ b/host/lib/usrp/b100/b100_ctrl.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/b100_iface.cpp b/host/lib/usrp/b100/b100_iface.cpp
index 7baa5da37..402560c33 100644
--- a/host/lib/usrp/b100/b100_iface.cpp
+++ b/host/lib/usrp/b100/b100_iface.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -15,7 +15,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "b100_iface.hpp"
+#include "b100_impl.hpp"
 #include "usrp_commands.h"
 #include <uhd/exception.hpp>
 #include <uhd/utils/byteswap.hpp>
@@ -38,8 +38,6 @@ using namespace uhd::transport;
  * Constants
  **********************************************************************/
 static const bool iface_debug = true;
-static const boost::uint16_t USRP_B_FW_COMPAT_NUM = 0x02;
-static const boost::uint16_t USRP_B_FPGA_COMPAT_NUM = 0x04;
 
 /***********************************************************************
  * I2C + FX2 implementation wrapper
@@ -117,21 +115,21 @@ public:
         const boost::uint16_t fw_compat_num = _fx2_ctrl->usrp_control_read(
             VRQ_FW_COMPAT, 0, 0, data, sizeof(data)
         );
-        if (fw_compat_num != USRP_B_FW_COMPAT_NUM){
+        if (fw_compat_num != B100_FW_COMPAT_NUM){
             throw uhd::runtime_error(str(boost::format(
                 "Expected firmware compatibility number 0x%x, but got 0x%x:\n"
                 "The firmware build is not compatible with the host code build."
-            ) % USRP_B_FW_COMPAT_NUM % fw_compat_num));
+            ) % B100_FW_COMPAT_NUM % fw_compat_num));
         }
     }
 
     void check_fpga_compat(void){
         const boost::uint16_t fpga_compat_num = this->peek16(B100_REG_MISC_COMPAT);
-        if (fpga_compat_num != USRP_B_FPGA_COMPAT_NUM){
+        if (fpga_compat_num != B100_FPGA_COMPAT_NUM){
             throw uhd::runtime_error(str(boost::format(
                 "Expected FPGA compatibility number 0x%x, but got 0x%x:\n"
                 "The FPGA build is not compatible with the host code build."
-            ) % USRP_B_FPGA_COMPAT_NUM % fpga_compat_num));
+            ) % B100_FPGA_COMPAT_NUM % fpga_compat_num));
         }
     }
 
diff --git a/host/lib/usrp/b100/b100_iface.hpp b/host/lib/usrp/b100/b100_iface.hpp
index 57ed6a45c..a98db98dc 100644
--- a/host/lib/usrp/b100/b100_iface.hpp
+++ b/host/lib/usrp/b100/b100_iface.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -45,6 +45,11 @@ public:
                      b100_ctrl::sptr fpga_ctrl = b100_ctrl::sptr()
     );
 
+    //! TODO implement this for multiple hardwares revs in the future
+    std::string get_cname(void){
+        return "USRP-B100";
+    }
+
     /*!
      * Reset the GPIF interface on the FX2
      * \param which endpoint to reset
diff --git a/host/lib/usrp/b100/b100_impl.cpp b/host/lib/usrp/b100/b100_impl.cpp
index 7e733ddd9..db7c585d7 100644
--- a/host/lib/usrp/b100/b100_impl.cpp
+++ b/host/lib/usrp/b100/b100_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -72,7 +72,7 @@ static device_addrs_t b100_find(const device_addr_t &hint)
         //extract the firmware path for the b100
         std::string b100_fw_image;
         try{
-            b100_fw_image = find_image_path(hint.get("fw", "usrp_b100_fw.ihx"));
+            b100_fw_image = find_image_path(hint.get("fw", B100_FW_FILE_NAME));
         }
         catch(...){
             UHD_MSG(warning) << boost::format(
@@ -132,7 +132,7 @@ static device::sptr b100_make(const device_addr_t &device_addr){
 
     //extract the FPGA path for the B100
     std::string b100_fpga_image = find_image_path(
-        device_addr.has_key("fpga")? device_addr["fpga"] : "usrp_b100_fpga.bin"
+        device_addr.has_key("fpga")? device_addr["fpga"] : B100_FPGA_FILE_NAME
     );
 
     //try to match the given device address with something on the USB bus
@@ -203,6 +203,14 @@ b100_impl::b100_impl(uhd::transport::usb_zero_copy::sptr data_transport,
                          const double master_clock_rate)
  : _data_transport(data_transport), _fx2_ctrl(fx2_ctrl)
 {
+    _recv_otw_type.width = 16;
+    _recv_otw_type.shift = 0;
+    _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN;
+
+    _send_otw_type.width = 16;
+    _send_otw_type.shift = 0;
+    _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN;
+
     //this is the handler object for FPGA control packets
     _fpga_ctrl = b100_ctrl::make(ctrl_transport);
 
@@ -224,10 +232,7 @@ b100_impl::b100_impl(uhd::transport::usb_zero_copy::sptr data_transport,
     dboard_init();
 
     //initialize the dsps
-    rx_ddc_init();
-
-    //initialize the dsps
-    tx_duc_init();
+    dsp_init();
 
     //init the subdev specs
     this->mboard_set(MBOARD_PROP_RX_SUBDEV_SPEC, subdev_spec_t());
diff --git a/host/lib/usrp/b100/b100_impl.hpp b/host/lib/usrp/b100/b100_impl.hpp
index daec70bca..9d4314694 100644
--- a/host/lib/usrp/b100/b100_impl.hpp
+++ b/host/lib/usrp/b100/b100_impl.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -34,6 +34,15 @@
 #ifndef INCLUDED_B100_IMPL_HPP
 #define INCLUDED_B100_IMPL_HPP
 
+static const std::string     B100_FW_FILE_NAME = "usrp_b100_fw.bin";
+static const std::string     B100_FPGA_FILE_NAME = "usrp_b100_fpga.bin";
+static const boost::uint16_t B100_FW_COMPAT_NUM = 0x02;
+static const boost::uint16_t B100_FPGA_COMPAT_NUM = 0x04;
+static const size_t          B100_NUM_RX_DSPS = 2;
+static const size_t          B100_NUM_TX_DSPS = 1;
+static const boost::uint32_t B100_DSP_SID_BASE = 2; //leave room for other dsp (increments by 1)
+static const boost::uint32_t B100_ASYNC_SID = 1;
+
 /*!
  * Make a b100 dboard interface.
  * \param iface the b100 interface object
@@ -113,9 +122,8 @@ private:
     //handle io stuff
     uhd::transport::zero_copy_if::sptr _data_transport;
     UHD_PIMPL_DECL(io_impl) _io_impl;
-    void update_transport_channel_mapping(void);
+    void update_xport_channel_mapping(void);
     void io_init(void);
-    void issue_stream_cmd(const uhd::stream_cmd_t &stream_cmd);
     void handle_overrun(size_t);
 
     //otw types
@@ -181,19 +189,20 @@ private:
     void tx_dboard_set(const wax::obj &, const wax::obj &);
     wax_obj_proxy::sptr _tx_dboard_proxy;
 
-    //rx ddc functions and settings
-    void rx_ddc_init(void);
-    void rx_ddc_get(const wax::obj &, wax::obj &);
-    void rx_ddc_set(const wax::obj &, const wax::obj &);
-    double _ddc_freq; size_t _ddc_decim;
-    wax_obj_proxy::sptr _rx_ddc_proxy;
-
-    //tx duc functions and settings
-    void tx_duc_init(void);
-    void tx_duc_get(const wax::obj &, wax::obj &);
-    void tx_duc_set(const wax::obj &, const wax::obj &);
-    double _duc_freq; size_t _duc_interp;
-    wax_obj_proxy::sptr _tx_duc_proxy;
+    //methods and shadows for the dsps
+    UHD_PIMPL_DECL(dsp_impl) _dsp_impl;
+    void dsp_init(void);
+    void issue_ddc_stream_cmd(const uhd::stream_cmd_t &, size_t);
+
+    //properties interface for ddc
+    void ddc_get(const wax::obj &, wax::obj &, size_t);
+    void ddc_set(const wax::obj &, const wax::obj &, size_t);
+    uhd::dict<std::string, wax_obj_proxy::sptr> _rx_dsp_proxies;
+
+    //properties interface for duc
+    void duc_get(const wax::obj &, wax::obj &, size_t);
+    void duc_set(const wax::obj &, const wax::obj &, size_t);
+    uhd::dict<std::string, wax_obj_proxy::sptr> _tx_dsp_proxies;
 
     //transports
     b100_ctrl::sptr _fpga_ctrl;
diff --git a/host/lib/usrp/b100/b100_regs.hpp b/host/lib/usrp/b100/b100_regs.hpp
index 010df283e..06288e875 100644
--- a/host/lib/usrp/b100/b100_regs.hpp
+++ b/host/lib/usrp/b100/b100_regs.hpp
@@ -17,7 +17,6 @@
 // Slave pointers
 
 #define B100_REG_SLAVE(n) ((n)<<7)
-#define B100_REG_SR_ADDR(n) ((B100_REG_SETTINGS_BASE) + (4*(n)))
 
 /////////////////////////////////////////////////////
 // Slave 0 -- Misc Regs
@@ -164,86 +163,113 @@
 // Output-only, no readback, 64 registers total
 //  Each register must be written 32 bits at a time
 //  First the address xxx_xx00 and then xxx_xx10
+// 64 total regs in address space
+#define B100_SR_RX_CTRL0 0       // 9 regs (+0 to +8)
+#define B100_SR_RX_DSP0 10       // 4 regs (+0 to +3)
+#define B100_SR_RX_CTRL1 16      // 9 regs (+0 to +8)
+#define B100_SR_RX_DSP1 26       // 4 regs (+0 to +3)
+#define B100_SR_TX_CTRL 32       // 4 regs (+0 to +3)
+#define B100_SR_TX_DSP 38        // 3 regs (+0 to +2)
 
-#define B100_REG_SETTINGS_BASE_ADDR(n) (B100_REG_SLAVE(8) + (4*(n)))
+#define B100_SR_TIME64 42        // 6 regs (+0 to +5)
+#define B100_SR_RX_FRONT 48      // 5 regs (+0 to +4)
+#define B100_SR_TX_FRONT 54      // 5 regs (+0 to +4)
 
-#define B100_REG_SR_MISC_TEST32        B100_REG_SETTINGS_BASE_ADDR(52)
+#define B100_SR_REG_TEST32 60    // 1 reg
+#define B100_SR_CLEAR_RX_FIFO 61 // 1 reg
+#define B100_SR_CLEAR_TX_FIFO 62 // 1 reg
+#define B100_SR_GLOBAL_RESET 63  // 1 reg
+
+#define B100_REG_SR_ADDR(n) (B100_REG_SLAVE(8) + (4*(n)))
+
+#define B100_REG_SR_MISC_TEST32        B100_REG_SR_ADDR(B100_SR_REG_TEST32)
+
+/////////////////////////////////////////////////
+// Magic reset regs
+////////////////////////////////////////////////
+#define B100_REG_CLEAR_RX           B100_REG_SR_ADDR(B100_SR_CLEAR_RX_FIFO)
+#define B100_REG_CLEAR_TX           B100_REG_SR_ADDR(B100_SR_CLEAR_RX_FIFO)
+#define B100_REG_GLOBAL_RESET       B100_REG_SR_ADDR(B100_SR_GLOBAL_RESET)
 
 /////////////////////////////////////////////////
 // DSP RX Regs
 ////////////////////////////////////////////////
-#define B100_REG_DSP_RX_ADDR(n)      (B100_REG_SETTINGS_BASE_ADDR(16) + (4*(n)))
-#define B100_REG_DSP_RX_FREQ         B100_REG_DSP_RX_ADDR(0)
-#define B100_REG_DSP_RX_SCALE_IQ     B100_REG_DSP_RX_ADDR(1)  // {scale_i,scale_q}
-#define B100_REG_DSP_RX_DECIM_RATE   B100_REG_DSP_RX_ADDR(2)  // hb and decim rate
-#define B100_REG_DSP_RX_DCOFFSET_I   B100_REG_DSP_RX_ADDR(3) // Bit 31 high sets fixed offset mode, using lower 14 bits, // otherwise it is automatic
-#define B100_REG_DSP_RX_DCOFFSET_Q   B100_REG_DSP_RX_ADDR(4) // Bit 31 high sets fixed offset mode, using lower 14 bits
-#define B100_REG_DSP_RX_MUX          B100_REG_DSP_RX_ADDR(5)
+#define B100_REG_DSP_RX_HELPER(which, offset) ((which == 0)? \
+    (B100_REG_SR_ADDR(B100_SR_RX_DSP0 + offset)) : \
+    (B100_REG_SR_ADDR(B100_SR_RX_DSP1 + offset)))
+
+#define B100_REG_DSP_RX_FREQ(which)       B100_REG_DSP_RX_HELPER(which, 0)
+#define B100_REG_DSP_RX_DECIM(which)      B100_REG_DSP_RX_HELPER(which, 2)
+#define B100_REG_DSP_RX_MUX(which)        B100_REG_DSP_RX_HELPER(which, 3)
+
+#define B100_FLAG_DSP_RX_MUX_SWAP_IQ   (1 << 0)
+#define B100_FLAG_DSP_RX_MUX_REAL_MODE (1 << 1)
 
 ///////////////////////////////////////////////////
-// VITA RX CTRL regs
+// RX CTRL regs
 ///////////////////////////////////////////////////
-// The following 3 are logically a single command register.
-// They are clocked into the underlying fifo when time_ticks is written.
-#define B100_REG_CTRL_RX_ADDR(n)           (B100_REG_SETTINGS_BASE_ADDR(0) + (4*(n)))
-#define B100_REG_CTRL_RX_STREAM_CMD        B100_REG_CTRL_RX_ADDR(0) // {now, chain, num_samples(30)
-#define B100_REG_CTRL_RX_TIME_SECS         B100_REG_CTRL_RX_ADDR(1)
-#define B100_REG_CTRL_RX_TIME_TICKS        B100_REG_CTRL_RX_ADDR(2)
-#define B100_REG_CTRL_RX_CLEAR_OVERRUN     B100_REG_CTRL_RX_ADDR(3) // write anything to clear overrun
-#define B100_REG_CTRL_RX_VRT_HEADER        B100_REG_CTRL_RX_ADDR(4) // word 0 of packet.  FPGA fills in packet counter
-#define B100_REG_CTRL_RX_VRT_STREAM_ID     B100_REG_CTRL_RX_ADDR(5) // word 1 of packet.
-#define B100_REG_CTRL_RX_VRT_TRAILER       B100_REG_CTRL_RX_ADDR(6)
-#define B100_REG_CTRL_RX_NSAMPS_PER_PKT    B100_REG_CTRL_RX_ADDR(7)
-#define B100_REG_CTRL_RX_NCHANNELS         B100_REG_CTRL_RX_ADDR(8) // 1 in basic case, up to 4 for vector sources
+#define B100_REG_RX_CTRL_HELPER(which, offset) ((which == 0)? \
+    (B100_REG_SR_ADDR(B100_SR_RX_CTRL0 + offset)) : \
+    (B100_REG_SR_ADDR(B100_SR_RX_CTRL1 + offset)))
+
+#define B100_REG_RX_CTRL_STREAM_CMD(which)     B100_REG_RX_CTRL_HELPER(which, 0)
+#define B100_REG_RX_CTRL_TIME_SECS(which)      B100_REG_RX_CTRL_HELPER(which, 1)
+#define B100_REG_RX_CTRL_TIME_TICKS(which)     B100_REG_RX_CTRL_HELPER(which, 2)
+#define B100_REG_RX_CTRL_CLEAR(which)          B100_REG_RX_CTRL_HELPER(which, 3)
+#define B100_REG_RX_CTRL_VRT_HDR(which)        B100_REG_RX_CTRL_HELPER(which, 4)
+#define B100_REG_RX_CTRL_VRT_SID(which)        B100_REG_RX_CTRL_HELPER(which, 5)
+#define B100_REG_RX_CTRL_VRT_TLR(which)        B100_REG_RX_CTRL_HELPER(which, 6)
+#define B100_REG_RX_CTRL_NSAMPS_PP(which)      B100_REG_RX_CTRL_HELPER(which, 7)
+#define B100_REG_RX_CTRL_NCHANNELS(which)      B100_REG_RX_CTRL_HELPER(which, 8)
 
 /////////////////////////////////////////////////
-// DSP TX Regs
+// RX FE
 ////////////////////////////////////////////////
-#define B100_REG_DSP_TX_ADDR(n)      (B100_REG_SETTINGS_BASE_ADDR(32) + (4*(n)))
-#define B100_REG_DSP_TX_FREQ         B100_REG_DSP_TX_ADDR(0)
-#define B100_REG_DSP_TX_SCALE_IQ     B100_REG_DSP_TX_ADDR(1) // {scale_i,scale_q}
-#define B100_REG_DSP_TX_INTERP_RATE  B100_REG_DSP_TX_ADDR(2)
-#define B100_REG_DSP_TX_UNUSED       B100_REG_DSP_TX_ADDR(3)
-#define B100_REG_DSP_TX_MUX          B100_REG_DSP_TX_ADDR(4)
+#define B100_REG_RX_FE_SWAP_IQ             B100_REG_SR_ADDR(B100_SR_RX_FRONT + 0) //lower bit
+#define B100_REG_RX_FE_MAG_CORRECTION      B100_REG_SR_ADDR(B100_SR_RX_FRONT + 1) //18 bits
+#define B100_REG_RX_FE_PHASE_CORRECTION    B100_REG_SR_ADDR(B100_SR_RX_FRONT + 2) //18 bits
+#define B100_REG_RX_FE_OFFSET_I            B100_REG_SR_ADDR(B100_SR_RX_FRONT + 3) //18 bits
+#define B100_REG_RX_FE_OFFSET_Q            B100_REG_SR_ADDR(B100_SR_RX_FRONT + 4) //18 bits
 
 /////////////////////////////////////////////////
-// VITA TX CTRL regs
+// DSP TX Regs
 ////////////////////////////////////////////////
-#define B100_REG_CTRL_TX_ADDR(n)           (B100_REG_SETTINGS_BASE_ADDR(24) + (4*(n)))
-#define B100_REG_CTRL_TX_NCHANNELS         B100_REG_CTRL_TX_ADDR(0)
-#define B100_REG_CTRL_TX_CLEAR_UNDERRUN    B100_REG_CTRL_TX_ADDR(1)
-#define B100_REG_CTRL_TX_REPORT_SID        B100_REG_CTRL_TX_ADDR(2)
-#define B100_REG_CTRL_TX_POLICY            B100_REG_CTRL_TX_ADDR(3)
+#define B100_REG_DSP_TX_FREQ          B100_REG_SR_ADDR(B100_SR_TX_DSP + 0)
+#define B100_REG_DSP_TX_SCALE_IQ      B100_REG_SR_ADDR(B100_SR_TX_DSP + 1)
+#define B100_REG_DSP_TX_INTERP_RATE   B100_REG_SR_ADDR(B100_SR_TX_DSP + 2)
 
-#define B100_FLAG_CTRL_TX_POLICY_WAIT          (0x1 << 0)
-#define B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET   (0x1 << 1)
-#define B100_FLAG_CTRL_TX_POLICY_NEXT_BURST    (0x1 << 2)
+///////////////////////////////////////////////////
+// TX CTRL regs
+///////////////////////////////////////////////////
+#define B100_REG_TX_CTRL_NUM_CHAN       B100_REG_SR_ADDR(B100_SR_TX_CTRL + 0)
+#define B100_REG_TX_CTRL_CLEAR_STATE    B100_REG_SR_ADDR(B100_SR_TX_CTRL + 1)
+#define B100_REG_TX_CTRL_REPORT_SID     B100_REG_SR_ADDR(B100_SR_TX_CTRL + 2)
+#define B100_REG_TX_CTRL_POLICY         B100_REG_SR_ADDR(B100_SR_TX_CTRL + 3)
+#define B100_REG_TX_CTRL_CYCLES_PER_UP  B100_REG_SR_ADDR(B100_SR_TX_CTRL + 4)
+#define B100_REG_TX_CTRL_PACKETS_PER_UP B100_REG_SR_ADDR(B100_SR_TX_CTRL + 5)
+
+#define B100_FLAG_TX_CTRL_POLICY_WAIT          (0x1 << 0)
+#define B100_FLAG_TX_CTRL_POLICY_NEXT_PACKET   (0x1 << 1)
+#define B100_FLAG_TX_CTRL_POLICY_NEXT_BURST    (0x1 << 2)
+
+/////////////////////////////////////////////////
+// TX FE
+////////////////////////////////////////////////
+#define B100_REG_TX_FE_DC_OFFSET_I         B100_REG_SR_ADDR(B100_SR_TX_FRONT + 0) //24 bits
+#define B100_REG_TX_FE_DC_OFFSET_Q         B100_REG_SR_ADDR(B100_SR_TX_FRONT + 1) //24 bits
+#define B100_REG_TX_FE_MAC_CORRECTION      B100_REG_SR_ADDR(B100_SR_TX_FRONT + 2) //18 bits
+#define B100_REG_TX_FE_PHASE_CORRECTION    B100_REG_SR_ADDR(B100_SR_TX_FRONT + 3) //18 bits
+#define B100_REG_TX_FE_MUX                 B100_REG_SR_ADDR(B100_SR_TX_FRONT + 4) //8 bits (std output = 0x10, reversed = 0x01)
 
 /////////////////////////////////////////////////
 // VITA49 64 bit time (write only)
 ////////////////////////////////////////////////
-  /*!
-   * \brief Time 64 flags
-   *
-   * <pre>
-   *
-   *    3                   2                   1
-   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
-   * +-----------------------------------------------------------+-+-+
-   * |                                                           |S|P|
-   * +-----------------------------------------------------------+-+-+
-   *
-   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
-   * S - Source (0=sma, 1=mimo, 0=default)
-   *
-   * </pre>
-   */
-#define B100_REG_TIME64_ADDR(n)     (B100_REG_SETTINGS_BASE_ADDR(40) + (4*(n)))
-#define B100_REG_TIME64_SECS  B100_REG_TIME64_ADDR(0)  // value to set absolute secs to on next PPS
-#define B100_REG_TIME64_TICKS B100_REG_TIME64_ADDR(1)  // value to set absolute ticks to on next PPS
-#define B100_REG_TIME64_FLAGS B100_REG_TIME64_ADDR(2)  // flags - see chart above
-#define B100_REG_TIME64_IMM   B100_REG_TIME64_ADDR(3)  // set immediate (0=latch on next pps, 1=latch immediate, default=0)
-#define B100_REG_TIME64_TPS   B100_REG_TIME64_ADDR(4)  // clock ticks per second (counter rollover)
+#define B100_REG_TIME64_SECS      B100_REG_SR_ADDR(B100_SR_TIME64 + 0)
+#define B100_REG_TIME64_TICKS     B100_REG_SR_ADDR(B100_SR_TIME64 + 1)
+#define B100_REG_TIME64_FLAGS     B100_REG_SR_ADDR(B100_SR_TIME64 + 2)
+#define B100_REG_TIME64_IMM       B100_REG_SR_ADDR(B100_SR_TIME64 + 3)
+#define B100_REG_TIME64_TPS       B100_REG_SR_ADDR(B100_SR_TIME64 + 4)
+#define B100_REG_TIME64_MIMO_SYNC B100_REG_SR_ADDR(B100_SR_TIME64 + 5)
 
 //pps flags (see above)
 #define B100_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
@@ -254,11 +280,5 @@
 #define B100_FLAG_TIME64_LATCH_NOW 1
 #define B100_FLAG_TIME64_LATCH_NEXT_PPS 0
 
-#define B100_REG_CLEAR_RX_FIFO     B100_REG_SETTINGS_BASE_ADDR(48)
-#define B100_REG_CLEAR_TX_FIFO     B100_REG_SETTINGS_BASE_ADDR(49)
-
-#define B100_REG_GLOBAL_RESET      B100_REG_SETTINGS_BASE_ADDR(50)
-#define B100_REG_TEST32            B100_REG_SETTINGS_BASE_ADDR(52)
-
 #endif
 
diff --git a/host/lib/usrp/b100/clock_ctrl.cpp b/host/lib/usrp/b100/clock_ctrl.cpp
index e138242d1..02091f00a 100644
--- a/host/lib/usrp/b100/clock_ctrl.cpp
+++ b/host/lib/usrp/b100/clock_ctrl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010-2011 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/clock_ctrl.hpp b/host/lib/usrp/b100/clock_ctrl.hpp
index 2a2e74024..3a24f2a66 100644
--- a/host/lib/usrp/b100/clock_ctrl.hpp
+++ b/host/lib/usrp/b100/clock_ctrl.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/codec_ctrl.cpp b/host/lib/usrp/b100/codec_ctrl.cpp
index 4d118b68b..7e9f355d4 100644
--- a/host/lib/usrp/b100/codec_ctrl.cpp
+++ b/host/lib/usrp/b100/codec_ctrl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/codec_ctrl.hpp b/host/lib/usrp/b100/codec_ctrl.hpp
index 1bd579190..9ef960592 100644
--- a/host/lib/usrp/b100/codec_ctrl.hpp
+++ b/host/lib/usrp/b100/codec_ctrl.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/codec_impl.cpp b/host/lib/usrp/b100/codec_impl.cpp
index de3ca3a66..a959c9d60 100644
--- a/host/lib/usrp/b100/codec_impl.cpp
+++ b/host/lib/usrp/b100/codec_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/ctrl_packet.hpp b/host/lib/usrp/b100/ctrl_packet.hpp
index f504fc5aa..bab1f0de1 100644
--- a/host/lib/usrp/b100/ctrl_packet.hpp
+++ b/host/lib/usrp/b100/ctrl_packet.hpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/dboard_iface.cpp b/host/lib/usrp/b100/dboard_iface.cpp
index ec3da6220..003d86d48 100644
--- a/host/lib/usrp/b100/dboard_iface.cpp
+++ b/host/lib/usrp/b100/dboard_iface.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/dboard_impl.cpp b/host/lib/usrp/b100/dboard_impl.cpp
index ba3776728..ed1d4bb1d 100644
--- a/host/lib/usrp/b100/dboard_impl.cpp
+++ b/host/lib/usrp/b100/dboard_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/host/lib/usrp/b100/dsp_impl.cpp b/host/lib/usrp/b100/dsp_impl.cpp
index c1bf6bedd..e27894c1a 100644
--- a/host/lib/usrp/b100/dsp_impl.cpp
+++ b/host/lib/usrp/b100/dsp_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -22,36 +22,80 @@
 #include <boost/math/special_functions/round.hpp>
 #include <boost/bind.hpp>
 
-#define rint boost::math::iround
-
 using namespace uhd;
 using namespace uhd::usrp;
 
-static const double MASTER_CLOCK_RATE = 64e6; //TODO get from clock control
+/***********************************************************************
+ * DSP impl and methods
+ **********************************************************************/
+struct b100_impl::dsp_impl{
+    uhd::dict<size_t, size_t> ddc_decim;
+    uhd::dict<size_t, double> ddc_freq;
+    uhd::dict<size_t, size_t> duc_interp;
+    uhd::dict<size_t, double> duc_freq;
+};
 
 /***********************************************************************
  * RX DDC Initialization
  **********************************************************************/
-void b100_impl::rx_ddc_init(void){
-    _rx_ddc_proxy = wax_obj_proxy::make(
-        boost::bind(&b100_impl::rx_ddc_get, this, _1, _2),
-        boost::bind(&b100_impl::rx_ddc_set, this, _1, _2)
-    );
-
-    //initial config and update
-    rx_ddc_set(DSP_PROP_FREQ_SHIFT, double(0));
-    rx_ddc_set(DSP_PROP_HOST_RATE, double(16e6));
+void b100_impl::dsp_init(void){
+    //create new dsp impl
+    _dsp_impl = UHD_PIMPL_MAKE(dsp_impl, ());
+
+    //bind and initialize the rx dsps
+    for (size_t i = 0; i < B100_NUM_RX_DSPS; i++){
+        _rx_dsp_proxies[str(boost::format("DSP%d")%i)] = wax_obj_proxy::make(
+            boost::bind(&b100_impl::ddc_get, this, _1, _2, i),
+            boost::bind(&b100_impl::ddc_set, this, _1, _2, i)
+        );
+
+        //initial config and update
+        ddc_set(DSP_PROP_FREQ_SHIFT, double(0), i);
+        ddc_set(DSP_PROP_HOST_RATE, double(_clock_ctrl->get_fpga_clock_rate()/16), i);
+
+        //setup the rx control registers
+        _iface->poke32(B100_REG_RX_CTRL_CLEAR(i), 1); //reset
+        _iface->poke32(B100_REG_RX_CTRL_NSAMPS_PP(i), this->get_max_recv_samps_per_packet());
+        _iface->poke32(B100_REG_RX_CTRL_NCHANNELS(i), 1);
+        _iface->poke32(B100_REG_RX_CTRL_VRT_HDR(i), 0
+            | (0x1 << 28) //if data with stream id
+            | (0x1 << 26) //has trailer
+            | (0x3 << 22) //integer time other
+            | (0x1 << 20) //fractional time sample count
+        );
+        _iface->poke32(B100_REG_RX_CTRL_VRT_SID(i), B100_DSP_SID_BASE + i);
+        _iface->poke32(B100_REG_RX_CTRL_VRT_TLR(i), 0);
+        _iface->poke32(B100_REG_TIME64_TPS, size_t(_clock_ctrl->get_fpga_clock_rate()));
+    }
+
+    //bind and initialize the tx dsps
+    for (size_t i = 0; i < B100_NUM_TX_DSPS; i++){
+        _tx_dsp_proxies[str(boost::format("DSP%d")%i)] = wax_obj_proxy::make(
+            boost::bind(&b100_impl::duc_get, this, _1, _2, i),
+            boost::bind(&b100_impl::duc_set, this, _1, _2, i)
+        );
+
+        //initial config and update
+        duc_set(DSP_PROP_FREQ_SHIFT, double(0), i);
+        duc_set(DSP_PROP_HOST_RATE, double(_clock_ctrl->get_fpga_clock_rate()/16), i);
+
+        //init the tx control registers
+        _iface->poke32(B100_REG_TX_CTRL_CLEAR_STATE, 1); //reset
+        _iface->poke32(B100_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
+        _iface->poke32(B100_REG_TX_CTRL_REPORT_SID, B100_ASYNC_SID);
+        _iface->poke32(B100_REG_TX_CTRL_POLICY, B100_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
+    }
 }
 
 /***********************************************************************
  * RX DDC Get
  **********************************************************************/
-void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){
+void b100_impl::ddc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
     case DSP_PROP_NAME:
-        val = std::string("USRP-B100 RX DSP");
+        val = str(boost::format("%s ddc%d") % _iface->get_cname() % which_dsp);
         return;
 
     case DSP_PROP_OTHERS:
@@ -59,7 +103,7 @@ void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){
         return;
 
     case DSP_PROP_FREQ_SHIFT:
-        val = _ddc_freq;
+        val = _dsp_impl->ddc_freq[which_dsp];
         return;
 
     case DSP_PROP_CODEC_RATE:
@@ -67,7 +111,7 @@ void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){
         return;
 
     case DSP_PROP_HOST_RATE:
-        val = _clock_ctrl->get_fpga_clock_rate()/_ddc_decim;
+        val = _clock_ctrl->get_fpga_clock_rate()/_dsp_impl->ddc_decim[which_dsp];
         return;
 
     default: UHD_THROW_PROP_GET_ERROR();
@@ -77,34 +121,31 @@ void b100_impl::rx_ddc_get(const wax::obj &key_, wax::obj &val){
 /***********************************************************************
  * RX DDC Set
  **********************************************************************/
-void b100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){
+void b100_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
+
     case DSP_PROP_STREAM_CMD:
-        issue_stream_cmd(val.as<stream_cmd_t>());
+        issue_ddc_stream_cmd(val.as<stream_cmd_t>(), which_dsp);
         return;
 
     case DSP_PROP_FREQ_SHIFT:{
             double new_freq = val.as<double>();
-            _iface->poke32(B100_REG_DSP_RX_FREQ,
+            _iface->poke32(B100_REG_DSP_RX_FREQ(which_dsp),
                 dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate())
             );
-            _ddc_freq = new_freq; //shadow
+            _dsp_impl->ddc_freq[which_dsp] = new_freq; //shadow
         }
         return;
 
     case DSP_PROP_HOST_RATE:{
-            //set the decimation
-            _ddc_decim = rint(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
-            _iface->poke32(B100_REG_DSP_RX_DECIM_RATE, dsp_type1::calc_cic_filter_word(_ddc_decim));
+            _dsp_impl->ddc_decim[which_dsp] = boost::math::iround(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
 
-            //set the scaling
-            static const boost::int16_t default_rx_scale_iq = 1024;
-            _iface->poke32(B100_REG_DSP_RX_SCALE_IQ,
-                dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
-            );
+            //set the decimation
+            _iface->poke32(B100_REG_DSP_RX_DECIM(which_dsp), dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp]));
         }
+        this->update_xport_channel_mapping(); //rate changed -> update
         return;
 
     default: UHD_THROW_PROP_SET_ERROR();
@@ -112,28 +153,14 @@ void b100_impl::rx_ddc_set(const wax::obj &key_, const wax::obj &val){
 }
 
 /***********************************************************************
- * TX DUC Initialization
- **********************************************************************/
-void b100_impl::tx_duc_init(void){
-    _tx_duc_proxy = wax_obj_proxy::make(
-        boost::bind(&b100_impl::tx_duc_get, this, _1, _2),
-        boost::bind(&b100_impl::tx_duc_set, this, _1, _2)
-    );
-
-    //initial config and update
-    tx_duc_set(DSP_PROP_FREQ_SHIFT, double(0));
-    tx_duc_set(DSP_PROP_HOST_RATE, double(16e6));
-}
-
-/***********************************************************************
  * TX DUC Get
  **********************************************************************/
-void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){
+void b100_impl::duc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
     case DSP_PROP_NAME:
-        val = std::string("USRP-B100 TX DSP");
+        val = str(boost::format("%s duc%d") % _iface->get_cname() % which_dsp);
         return;
 
     case DSP_PROP_OTHERS:
@@ -141,7 +168,7 @@ void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){
         return;
 
     case DSP_PROP_FREQ_SHIFT:
-        val = _duc_freq;
+        val = _dsp_impl->duc_freq[which_dsp];
         return;
 
     case DSP_PROP_CODEC_RATE:
@@ -149,7 +176,7 @@ void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){
         return;
 
     case DSP_PROP_HOST_RATE:
-        val = _clock_ctrl->get_fpga_clock_rate()/_duc_interp;
+        val = _clock_ctrl->get_fpga_clock_rate()/_dsp_impl->duc_interp[which_dsp];
         return;
 
     default: UHD_THROW_PROP_GET_ERROR();
@@ -159,7 +186,7 @@ void b100_impl::tx_duc_get(const wax::obj &key_, wax::obj &val){
 /***********************************************************************
  * TX DUC Set
  **********************************************************************/
-void b100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){
+void b100_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
@@ -169,19 +196,20 @@ void b100_impl::tx_duc_set(const wax::obj &key_, const wax::obj &val){
             _iface->poke32(B100_REG_DSP_TX_FREQ,
                 dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate())
             );
-            _duc_freq = new_freq; //shadow
+            _dsp_impl->duc_freq[which_dsp] = new_freq; //shadow
         }
         return;
 
     case DSP_PROP_HOST_RATE:{
-            _duc_interp = rint(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
+            _dsp_impl->duc_interp[which_dsp] = boost::math::iround(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
 
             //set the interpolation
-            _iface->poke32(B100_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_duc_interp));
+            _iface->poke32(B100_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_dsp_impl->duc_interp[which_dsp]));
 
             //set the scaling
-            _iface->poke32(B100_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_duc_interp));
+            _iface->poke32(B100_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp]));
         }
+        this->update_xport_channel_mapping(); //rate changed -> update
         return;
 
     default: UHD_THROW_PROP_SET_ERROR();
diff --git a/host/lib/usrp/b100/io_impl.cpp b/host/lib/usrp/b100/io_impl.cpp
index 3978bea75..5377c43d5 100644
--- a/host/lib/usrp/b100/io_impl.cpp
+++ b/host/lib/usrp/b100/io_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -45,17 +45,45 @@ struct b100_impl::io_impl{
     io_impl(zero_copy_if::sptr data_transport):
         data_transport(data_transport)
     {
-        /* NOP */
+        for (size_t i = 0; i < B100_NUM_RX_DSPS; i++){
+            typedef bounded_buffer<managed_recv_buffer::sptr> buffs_queue_type;
+            _buffs_queue.push_back(new buffs_queue_type(data_transport->get_num_recv_frames()));
+        }
     }
 
     ~io_impl(void){
-        //drain the rx buffs
-        //while(data_transport->get_recv_buff().get() != NULL){
-                /* NOP */
-        //}
+        for (size_t i = 0; i < _buffs_queue.size(); i++){
+            delete _buffs_queue[i];
+        }
     }
 
-    zero_copy_if::sptr &data_transport;
+    zero_copy_if::sptr data_transport;
+
+    std::vector<bounded_buffer<managed_recv_buffer::sptr> *> _buffs_queue;
+
+    //gets buffer, determines if its the requested index,
+    //and either queues the buffer or returns the buffer
+    managed_recv_buffer::sptr get_recv_buff(const size_t index, const double timeout){
+        while (true){
+            managed_recv_buffer::sptr buff;
+
+            //attempt to pop a buffer from the queue
+            if (_buffs_queue[index]->pop_with_haste(buff)) return buff;
+
+            //otherwise, call into the transport
+            buff = data_transport->get_recv_buff(timeout);
+            if (buff.get() == NULL) return buff; //timeout
+
+            //check the stream id to know which channel
+            const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>();
+            const size_t rx_index = uhd::wtohx(vrt_hdr[1]) - B100_DSP_SID_BASE;
+            if (rx_index == index) return buff; //got expected message
+
+            //otherwise queue and try again
+            if (rx_index < B100_NUM_RX_DSPS) _buffs_queue[rx_index]->push_with_pop_on_full(buff);
+            else UHD_MSG(error) << "Got a data packet with known SID " << uhd::wtohx(vrt_hdr[1]) << std::endl;
+        }
+    }
 
     sph::recv_packet_handler recv_handler;
     sph::send_packet_handler send_handler;
@@ -66,46 +94,17 @@ struct b100_impl::io_impl{
  * Initialize internals within this file
  **********************************************************************/
 void b100_impl::io_init(void){
-    _recv_otw_type.width = 16;
-    _recv_otw_type.shift = 0;
-    _recv_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN;
-
-    _send_otw_type.width = 16;
-    _send_otw_type.shift = 0;
-    _send_otw_type.byteorder = otw_type_t::BO_LITTLE_ENDIAN;
-    
     _iface->reset_gpif(6);
 
-    //reset state machines
-    _iface->poke32(B100_REG_CTRL_TX_CLEAR_UNDERRUN, 0);
-    _iface->poke32(B100_REG_CTRL_RX_CLEAR_OVERRUN, 0);
-
     _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_transport));
-    
-    //setup rx data path
-    _iface->poke32(B100_REG_CTRL_RX_NSAMPS_PER_PKT, get_max_recv_samps_per_packet());
-    UHD_LOGV(always) << "IO: Using " << get_max_recv_samps_per_packet() << " samples per packet" << std::endl;
-    _iface->poke32(B100_REG_CTRL_RX_NCHANNELS, 1);
-    _iface->poke32(B100_REG_CTRL_RX_VRT_HEADER, 0
-        | (0x1 << 28) //if data with stream id
-        | (0x1 << 26) //has trailer
-        | (0x3 << 22) //integer time other
-        | (0x1 << 20) //fractional time sample count
-    );
-    _iface->poke32(B100_REG_CTRL_RX_VRT_TRAILER, 0);
 
-    //set the streamid to reset the seq num
-    _iface->poke32(B100_REG_CTRL_TX_REPORT_SID, 0);
-    //setup the tx policy
-    _iface->poke32(B100_REG_CTRL_TX_POLICY, B100_FLAG_CTRL_TX_POLICY_NEXT_PACKET);
-    
     //set the expected packet size in USB frames
     _iface->poke32(B100_REG_MISC_RX_LEN, 4);
 
-    update_transport_channel_mapping();
+    update_xport_channel_mapping();
 }
 
-void b100_impl::update_transport_channel_mapping(void){
+void b100_impl::update_xport_channel_mapping(void){
     if (_io_impl.get() == NULL) return; //not inited yet
 
     //set all of the relevant properties on the handler
@@ -113,10 +112,11 @@ void b100_impl::update_transport_channel_mapping(void){
     _io_impl->recv_handler.resize(_rx_subdev_spec.size());
     _io_impl->recv_handler.set_vrt_unpacker(&vrt::if_hdr_unpack_le);
     _io_impl->recv_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate());
-    _io_impl->recv_handler.set_samp_rate(_rx_ddc_proxy->get_link()[DSP_PROP_HOST_RATE].as<double>());
+    //FIXME assumes homogeneous rates across all dsp
+    _io_impl->recv_handler.set_samp_rate(_rx_dsp_proxies[_rx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as<double>());
     for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){
         _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind(
-            &uhd::transport::zero_copy_if::get_recv_buff, _io_impl->data_transport, _1
+            &b100_impl::io_impl::get_recv_buff, _io_impl.get(), chan, _1
         ));
         _io_impl->recv_handler.set_overflow_handler(chan, boost::bind(
             &b100_impl::handle_overrun, this, chan
@@ -129,7 +129,8 @@ void b100_impl::update_transport_channel_mapping(void){
     _io_impl->send_handler.resize(_tx_subdev_spec.size());
     _io_impl->send_handler.set_vrt_packer(&vrt::if_hdr_pack_le);
     _io_impl->send_handler.set_tick_rate(_clock_ctrl->get_fpga_clock_rate());
-    _io_impl->send_handler.set_samp_rate(_tx_duc_proxy->get_link()[DSP_PROP_HOST_RATE].as<double>());
+    //FIXME assumes homogeneous rates across all dsp
+    _io_impl->send_handler.set_samp_rate(_tx_dsp_proxies[_tx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as<double>());
     for (size_t chan = 0; chan < _io_impl->send_handler.size(); chan++){
         _io_impl->send_handler.set_xport_chan_get_buff(chan, boost::bind(
             &uhd::transport::zero_copy_if::get_send_buff, _io_impl->data_transport, _1
@@ -155,7 +156,7 @@ size_t b100_impl::send(
     const send_buffs_type &buffs, size_t nsamps_per_buff,
     const tx_metadata_t &metadata, const io_type_t &io_type,
     send_mode_t send_mode, double timeout
-){    
+){
     return _io_impl->send_handler.send(
         buffs, nsamps_per_buff,
         metadata, io_type,
@@ -189,13 +190,13 @@ size_t b100_impl::recv(
     );
 }
 
-void b100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd)
+void b100_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, size_t index)
 {
     _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
-    _iface->poke32(B100_REG_CTRL_RX_STREAM_CMD, dsp_type1::calc_stream_cmd_word(stream_cmd));
-    _iface->poke32(B100_REG_CTRL_RX_TIME_SECS,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
-    _iface->poke32(B100_REG_CTRL_RX_TIME_TICKS, stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
-    
+    _iface->poke32(B100_REG_RX_CTRL_STREAM_CMD(index), dsp_type1::calc_stream_cmd_word(stream_cmd));
+    _iface->poke32(B100_REG_RX_CTRL_TIME_SECS(index),  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+    _iface->poke32(B100_REG_RX_CTRL_TIME_TICKS(index), stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
+
     if (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS) {
         while(_io_impl->data_transport->get_recv_buff().get() != NULL){
             /* NOP */
@@ -203,8 +204,8 @@ void b100_impl::issue_stream_cmd(const stream_cmd_t &stream_cmd)
     }
 }
 
-void b100_impl::handle_overrun(size_t){
+void b100_impl::handle_overrun(size_t index){
     if (_io_impl->continuous_streaming){
-        this->issue_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
+        this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS, index);
     }
 }
diff --git a/host/lib/usrp/b100/mboard_impl.cpp b/host/lib/usrp/b100/mboard_impl.cpp
index f9807e348..4f7dc8fce 100644
--- a/host/lib/usrp/b100/mboard_impl.cpp
+++ b/host/lib/usrp/b100/mboard_impl.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright 2010 Ettus Research LLC
+// Copyright 2011 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -90,7 +90,7 @@ void b100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
     //handle the get request conditioned on the key
     switch(key.as<mboard_prop_t>()){
     case MBOARD_PROP_NAME:
-        val = std::string("USRP-B100 mboard");
+        val = std::string(_iface->get_cname() + " mboard");
         return;
 
     case MBOARD_PROP_OTHERS:
@@ -116,21 +116,19 @@ void b100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
         return;
 
     case MBOARD_PROP_RX_DSP:
-        UHD_ASSERT_THROW(key.name == "");
-        val = _rx_ddc_proxy->get_link();
+        val = _rx_dsp_proxies[key.name]->get_link();
         return;
 
     case MBOARD_PROP_RX_DSP_NAMES:
-        val = prop_names_t(1, "");
+        val = _rx_dsp_proxies.keys();
         return;
 
     case MBOARD_PROP_TX_DSP:
-        UHD_ASSERT_THROW(key.name == "");
-        val = _tx_duc_proxy->get_link();
+        val = _tx_dsp_proxies[key.name]->get_link();
         return;
 
     case MBOARD_PROP_TX_DSP_NAMES:
-        val = prop_names_t(1, "");
+        val = _tx_dsp_proxies.keys();
         return;
 
     case MBOARD_PROP_CLOCK_CONFIG:
@@ -199,22 +197,59 @@ void b100_impl::mboard_set(const wax::obj &key, const wax::obj &val)
         }
         return;
 
-    case MBOARD_PROP_RX_SUBDEV_SPEC:
+    case MBOARD_PROP_RX_SUBDEV_SPEC:{
         _rx_subdev_spec = val.as<subdev_spec_t>();
         verify_rx_subdev_spec(_rx_subdev_spec, _mboard_proxy->get_link());
-        UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1);
-        //set the mux
-        _iface->poke32(B100_REG_DSP_RX_MUX, dsp_type1::calc_rx_mux_word(
-            _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
-        ));
-        return;
+        //sanity check
+        UHD_ASSERT_THROW(_rx_subdev_spec.size() <= B100_NUM_RX_DSPS);
+
+        //determine frontend swap IQ from the first channel
+        bool fe_swap_iq = false;
+        switch(_dboard_manager->get_rx_subdev(_rx_subdev_spec.at(0).sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()){
+        case SUBDEV_CONN_COMPLEX_QI:
+        case SUBDEV_CONN_REAL_Q:
+            fe_swap_iq = true;
+            break;
+        default: fe_swap_iq = false;
+        }
+        _iface->poke32(B100_REG_RX_FE_SWAP_IQ, fe_swap_iq? 1 : 0);
+
+        //set the dsp mux for each channel
+        for (size_t i = 0; i < _rx_subdev_spec.size(); i++){
+            bool iq_swap = false, real_mode = false;
+            switch(_dboard_manager->get_rx_subdev(_rx_subdev_spec.at(i).sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()){
+            case SUBDEV_CONN_COMPLEX_IQ:
+                iq_swap = fe_swap_iq;
+                real_mode = false;
+                break;
+            case SUBDEV_CONN_COMPLEX_QI:
+                iq_swap = not fe_swap_iq;
+                real_mode = false;
+                break;
+            case SUBDEV_CONN_REAL_I:
+                iq_swap = fe_swap_iq;
+                real_mode = true;
+                break;
+            case SUBDEV_CONN_REAL_Q:
+                iq_swap = not fe_swap_iq;
+                real_mode = true;
+                break;
+            }
+            _iface->poke32(B100_REG_DSP_RX_MUX(i),
+                (iq_swap?   B100_FLAG_DSP_RX_MUX_SWAP_IQ   : 0) |
+                (real_mode? B100_FLAG_DSP_RX_MUX_REAL_MODE : 0)
+            );
+        }
+        this->update_xport_channel_mapping();
+    }return;
 
     case MBOARD_PROP_TX_SUBDEV_SPEC:
         _tx_subdev_spec = val.as<subdev_spec_t>();
         verify_tx_subdev_spec(_tx_subdev_spec, _mboard_proxy->get_link());
-        UHD_ASSERT_THROW(_tx_subdev_spec.size() == 1);
-        //set the mux and set the number of tx channels
-        _iface->poke32(B100_REG_DSP_TX_MUX, dsp_type1::calc_tx_mux_word(
+        //sanity check
+        UHD_ASSERT_THROW(_tx_subdev_spec.size() <= B100_NUM_TX_DSPS);
+        //set the mux
+        _iface->poke32(B100_REG_TX_FE_MUX, dsp_type1::calc_tx_mux_word(
             _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
         ));
         return;
@@ -239,7 +274,7 @@ void b100_impl::mboard_set(const wax::obj &key, const wax::obj &val)
             << "See the application notes for USRP-B100 for further instructions.\n"
         ;
         _clock_ctrl->set_fpga_clock_rate(val.as<double>());
-        update_transport_channel_mapping();
+        update_xport_channel_mapping();
         return;
 
     default: UHD_THROW_PROP_SET_ERROR();
diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/usrp_e100/io_impl.cpp
index 4364f131f..f590951dc 100644
--- a/host/lib/usrp/usrp_e100/io_impl.cpp
+++ b/host/lib/usrp/usrp_e100/io_impl.cpp
@@ -126,7 +126,7 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(
 
         //handle an rx data packet or inline message
         const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>();
-        const size_t rx_index = vrt_hdr[1] - E100_DSP_SID_BASE;
+        const size_t rx_index = uhd::wtohx(vrt_hdr[1]) - E100_DSP_SID_BASE;
         if (rx_index < E100_NUM_RX_DSPS){
             debug_print_buff("data", buff);
             recv_pirate_booty[rx_index]->push_with_wait(buff);