Added support to set GPIO pins from dboard interface:

	write gpio and set pin control (atr or gpio)

Added property to get dboard interface from the dboard obj.

8 files changed, 48 insertions, 16 deletions

diff --git a/host/lib/usrp/dboard/db_rfx.cpp b/host/lib/usrp/dboard/db_rfx.cpp
index 7bfd14943..89e707718 100644
--- a/host/lib/usrp/dboard/db_rfx.cpp
+++ b/host/lib/usrp/dboard/db_rfx.cpp
@@ -176,8 +176,10 @@ rfx_xcvr::rfx_xcvr(
     this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
     this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
 
-    //set the gpio directions
+    //set the gpio directions and atr controls (identically)
     boost::uint16_t output_enables = POWER_IO | ANTSW_IO | MIXER_IO;
+    this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, output_enables);
+    this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, output_enables);
     this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, output_enables);
     this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, output_enables);
 
diff --git a/host/lib/usrp/dboard/db_wbx.cpp b/host/lib/usrp/dboard/db_wbx.cpp
index 81edf7a11..23654860f 100644
--- a/host/lib/usrp/dboard/db_wbx.cpp
+++ b/host/lib/usrp/dboard/db_wbx.cpp
@@ -164,7 +164,9 @@ wbx_xcvr::wbx_xcvr(
     this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
     this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);
 
-    //set the gpio directions
+    //set the gpio directions and atr controls (identically)
+    this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, TXIO_MASK);
+    this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, RXIO_MASK);
     this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK);
     this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK);
     if (wbx_debug) std::cerr << boost::format(
diff --git a/host/lib/usrp/dboard/db_xcvr2450.cpp b/host/lib/usrp/dboard/db_xcvr2450.cpp
index 3472229f4..d4d5f184e 100644
--- a/host/lib/usrp/dboard/db_xcvr2450.cpp
+++ b/host/lib/usrp/dboard/db_xcvr2450.cpp
@@ -169,7 +169,9 @@ xcvr2450::xcvr2450(ctor_args_t args) : xcvr_dboard_base(args){
     //enable only the clocks we need
     this->get_iface()->set_clock_enabled(dboard_iface::UNIT_TX, true);
 
-    //set the gpio directions
+    //set the gpio directions and atr controls (identically)
+    this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_TX, TXIO_MASK);
+    this->get_iface()->set_pin_ctrl(dboard_iface::UNIT_RX, RXIO_MASK);
     this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_TX, TXIO_MASK);
     this->get_iface()->set_gpio_ddr(dboard_iface::UNIT_RX, RXIO_MASK);
 
diff --git a/host/lib/usrp/dboard_manager.cpp b/host/lib/usrp/dboard_manager.cpp
index 8161727e5..01352039e 100644
--- a/host/lib/usrp/dboard_manager.cpp
+++ b/host/lib/usrp/dboard_manager.cpp
@@ -298,7 +298,8 @@ void dboard_manager_impl::set_nice_dboard_if(void){
     //set nice settings on each unit
     BOOST_FOREACH(dboard_iface::unit_t unit, units){
         _iface->set_gpio_ddr(unit, 0x0000); //all inputs
-        _iface->set_atr_reg(unit, dboard_iface::ATR_REG_IDLE, 0x0000); //all low
+        _iface->write_gpio(unit, 0x0000); //all low
+        _iface->set_pin_ctrl(unit, 0x0000); //all gpio
         _iface->set_clock_enabled(unit, false); //clock off
     }
 }
diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp
index d33a11fd6..0a2e4b550 100644
--- a/host/lib/usrp/usrp2/dboard_iface.cpp
+++ b/host/lib/usrp/usrp2/dboard_iface.cpp
@@ -39,8 +39,10 @@ public:
     void write_aux_dac(unit_t, int, float);
     float read_aux_adc(unit_t, int);
 
+    void set_pin_ctrl(unit_t, boost::uint16_t);
     void set_atr_reg(unit_t, atr_reg_t, boost::uint16_t);
     void set_gpio_ddr(unit_t, boost::uint16_t);
+    void write_gpio(unit_t, boost::uint16_t);
     boost::uint16_t read_gpio(unit_t);
 
     void write_i2c(boost::uint8_t, const byte_vector_t &);
@@ -68,6 +70,7 @@ private:
     usrp2_iface::sptr _iface;
     clock_ctrl::sptr _clock_ctrl;
     boost::uint32_t _ddr_shadow;
+    boost::uint32_t _gpio_shadow;
 
     uhd::dict<unit_t, ad5624_regs_t> _dac_regs;
     void _write_aux_dac(unit_t);
@@ -90,14 +93,7 @@ usrp2_dboard_iface::usrp2_dboard_iface(usrp2_iface::sptr iface, clock_ctrl::sptr
     _iface = iface;
     _clock_ctrl = clock_ctrl;
     _ddr_shadow = 0;
-
-    //set the selection mux to use atr
-    boost::uint32_t new_sels = 0x0;
-    for(size_t i = 0; i < 16; i++){
-        new_sels |= FRF_GPIO_SEL_ATR << (i*2);
-    }
-    _iface->poke32(FR_GPIO_TX_SEL, new_sels);
-    _iface->poke32(FR_GPIO_RX_SEL, new_sels);
+    _gpio_shadow = 0;
 
     //reset the aux dacs
     _dac_regs[UNIT_RX] = ad5624_regs_t();
@@ -136,6 +132,21 @@ static const uhd::dict<dboard_iface::unit_t, int> unit_to_shift = map_list_of
     (dboard_iface::UNIT_TX, 16)
 ;
 
+void usrp2_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint16_t value){
+    //calculate the new selection mux setting
+    boost::uint32_t new_sels = 0x0;
+    for(size_t i = 0; i < 16; i++){
+        bool is_bit_set = bool(value & (0x1 << i));
+        new_sels |= ((is_bit_set)? FRF_GPIO_SEL_ATR : FRF_GPIO_SEL_GPIO) << (i*2);
+    }
+
+    //write the selection mux value to register
+    switch(unit){
+    case UNIT_RX: _iface->poke32(FR_GPIO_RX_SEL, new_sels); return;
+    case UNIT_TX: _iface->poke32(FR_GPIO_TX_SEL, new_sels); return;
+    }
+}
+
 void usrp2_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){
     _ddr_shadow = \
         (_ddr_shadow & ~(0xffff << unit_to_shift[unit])) |
@@ -143,6 +154,13 @@ void usrp2_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint16_t value){
     _iface->poke32(FR_GPIO_DDR, _ddr_shadow);
 }
 
+void usrp2_dboard_iface::write_gpio(unit_t unit, boost::uint16_t value){
+    _gpio_shadow = \
+        (_gpio_shadow & ~(0xffff << unit_to_shift[unit])) |
+        (boost::uint32_t(value) << unit_to_shift[unit]);
+    _iface->poke32(FR_GPIO_IO, _gpio_shadow);
+}
+
 boost::uint16_t usrp2_dboard_iface::read_gpio(unit_t unit){
     return boost::uint16_t(_iface->peek32(FR_GPIO_IO) >> unit_to_shift[unit]);
 }
diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp
index 0f8a739f2..0ac39d2a3 100644
--- a/host/lib/usrp/usrp2/dboard_impl.cpp
+++ b/host/lib/usrp/usrp2/dboard_impl.cpp
@@ -38,9 +38,7 @@ void usrp2_impl::dboard_init(void){
     _tx_db_eeprom = dboard_eeprom_t(_iface->read_eeprom(I2C_ADDR_TX_DB, 0, dboard_eeprom_t::num_bytes()));
 
     //create a new dboard interface and manager
-    dboard_iface::sptr _dboard_iface(
-        make_usrp2_dboard_iface(_iface, _clock_ctrl)
-    );
+    _dboard_iface = make_usrp2_dboard_iface(_iface, _clock_ctrl);
     _dboard_manager = dboard_manager::make(
         _rx_db_eeprom.id, _tx_db_eeprom.id, _dboard_iface
     );
@@ -123,6 +121,10 @@ void usrp2_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
         val = _rx_db_eeprom.id;
         return;
 
+    case DBOARD_PROP_DBOARD_IFACE:
+        val = _dboard_iface;
+        return;
+
     default: UHD_THROW_PROP_GET_ERROR();
     }
 }
@@ -172,6 +174,10 @@ void usrp2_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
         val = _tx_db_eeprom.id;
         return;
 
+    case DBOARD_PROP_DBOARD_IFACE:
+        val = _dboard_iface;
+        return;
+
     default: UHD_THROW_PROP_GET_ERROR();
     }
 }
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index afea9683c..7948a2069 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -169,6 +169,7 @@ private:
 
     //rx and tx dboard methods and objects
     uhd::usrp::dboard_manager::sptr _dboard_manager;
+    uhd::usrp::dboard_iface::sptr _dboard_iface;
     void dboard_init(void);
 
     //properties for the mboard
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index feeccaa34..0f675357b 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -204,7 +204,7 @@
 #define FR_GPIO_RX_SEL     FR_GPIO_BASE + 12 // 16 2-bit fields select which source goes to RX DB
 
 // each 2-bit sel field is layed out this way
-#define FRF_GPIO_SEL_SW        0 // if pin is an output, set by software in the io reg
+#define FRF_GPIO_SEL_GPIO      0 // if pin is an output, set by GPIO register
 #define FRF_GPIO_SEL_ATR       1 // if pin is an output, set by ATR logic
 #define FRF_GPIO_SEL_DEBUG_0   2 // if pin is an output, debug lines from FPGA fabric
 #define FRF_GPIO_SEL_DEBUG_1   3 // if pin is an output, debug lines from FPGA fabric