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| author | vkakade <virendra.kakade@ni.com> | 2016-09-19 14:02:01 -0500 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2016-09-20 17:33:12 -0700 |
| commit | ce6be04bc75f5dda2943fd438c055c57b70a11a6 (patch) | |
| tree | 01dec5954ec65c39324c7b93af1390e6892faa51 /host/lib/usrp | |
| parent | 23cd2754e816f055accf3c3c049476a6668c52a1 (diff) | |
| download | uhd-ce6be04bc75f5dda2943fd438c055c57b70a11a6.tar.gz uhd-ce6be04bc75f5dda2943fd438c055c57b70a11a6.tar.bz2 uhd-ce6be04bc75f5dda2943fd438c055c57b70a11a6.zip | |
Added NI product IDs for USRP-2945 and USRP-2955
These are USRP RIO (X310) devices with TwinRX daughter-boards.
Diffstat (limited to 'host/lib/usrp')
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.cpp | 4 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_regs.hpp | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index 7f7fcad09..0cdc7a3b3 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -1664,6 +1664,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res case X310_2943R_40MHz_PCIE_SSID_ADC_18: case X310_2943R_120MHz_PCIE_SSID_ADC_18: case X310_2944R_40MHz_PCIE_SSID_ADC_18: + case X310_2945R_PCIE_SSID_ADC_18: case X310_2950R_40MHz_PCIE_SSID_ADC_18: case X310_2950R_120MHz_PCIE_SSID_ADC_18: case X310_2952R_40MHz_PCIE_SSID_ADC_18: @@ -1671,6 +1672,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res case X310_2953R_40MHz_PCIE_SSID_ADC_18: case X310_2953R_120MHz_PCIE_SSID_ADC_18: case X310_2954R_40MHz_PCIE_SSID_ADC_18: + case X310_2955R_PCIE_SSID_ADC_18: mb_type = USRP_X310_MB; break; default: mb_type = UNKNOWN; break; @@ -1721,6 +1723,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo case X310_2943R_40MHz_PCIE_SSID_ADC_18: case X310_2943R_120MHz_PCIE_SSID_ADC_18: case X310_2944R_40MHz_PCIE_SSID_ADC_18: + case X310_2945R_PCIE_SSID_ADC_18: case X310_2950R_40MHz_PCIE_SSID_ADC_18: case X310_2950R_120MHz_PCIE_SSID_ADC_18: case X310_2952R_40MHz_PCIE_SSID_ADC_18: @@ -1728,6 +1731,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo case X310_2953R_40MHz_PCIE_SSID_ADC_18: case X310_2953R_120MHz_PCIE_SSID_ADC_18: case X310_2954R_40MHz_PCIE_SSID_ADC_18: + case X310_2955R_PCIE_SSID_ADC_18: mb_type = USRP_X310_MB; break; default: UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl; diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp index c5ed1460b..80d275949 100644 --- a/host/lib/usrp/x300/x300_regs.hpp +++ b/host/lib/usrp/x300/x300_regs.hpp @@ -104,6 +104,7 @@ static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_18 = 0x785C; static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_18 = 0x7855; static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_18 = 0x785D; static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_18 = 0x7856; +static const uint32_t X310_2945R_PCIE_SSID_ADC_18 = 0x78EF; static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_18 = 0x7857; static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_18 = 0x785E; static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_18 = 0x7858; @@ -111,6 +112,7 @@ static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_18 = 0x785F; static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_18 = 0x7859; static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_18 = 0x7860; static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_18 = 0x785A; +static const uint32_t X310_2955R_PCIE_SSID_ADC_18 = 0x78F0; static const uint32_t FPGA_X3xx_SIG_VALUE = 0x58333030; |