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| author | Martin Braun <martin.braun@ettus.com> | 2015-03-31 09:24:21 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2015-03-31 09:24:21 -0700 |
| commit | 49489a56240ac9593330a3c56b5aefdf8c609a07 (patch) | |
| tree | bd01f891fdbcde86e564443238ec66e3d91a2bc3 /host/lib/usrp | |
| parent | 8c20712d611a8ac842984953f9924f30976fe884 (diff) | |
| parent | da5311407bdabcb7206f8ffb0b77de32d294f083 (diff) | |
| download | uhd-49489a56240ac9593330a3c56b5aefdf8c609a07.tar.gz uhd-49489a56240ac9593330a3c56b5aefdf8c609a07.tar.bz2 uhd-49489a56240ac9593330a3c56b5aefdf8c609a07.zip | |
Merge branch 'maint'
Conflicts:
host/docs/usrp_e3x0.dox
Diffstat (limited to 'host/lib/usrp')
| -rw-r--r-- | host/lib/usrp/dboard/db_tvrx2.cpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/dboard/db_tvrx2.cpp b/host/lib/usrp/dboard/db_tvrx2.cpp index 9300483d1..00c2fef50 100644 --- a/host/lib/usrp/dboard/db_tvrx2.cpp +++ b/host/lib/usrp/dboard/db_tvrx2.cpp @@ -1014,7 +1014,7 @@ tvrx2::tvrx2(ctor_args_t args) : rx_dboard_base(args){ _freq_scalar = (6*16.0e6)/this->get_iface()->get_clock_rate(dboard_iface::UNIT_RX); } else if (ref_clock == 200e6) { - UHD_MSG(warning) << boost::format("ref_clock was 200e6, setting ref_clock divider for 100e6.") % ref_clock << std::endl; + UHD_MSG(warning) << boost::format("ref_clock was 200e6, setting ref_clock divider for 100e6.") << std::endl; this->get_iface()->set_clock_rate(dboard_iface::UNIT_RX, 100e6); this->get_iface()->set_gpio_out(dboard_iface::UNIT_RX, REFCLOCK_DIV6); diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index 247c10ac4..b59247d53 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -190,7 +190,7 @@ void set_master_clock_rate(double clock_rate) { // PLL1 - 2 MHz compare frequency _lmk04816_regs.PLL1_N_28 = 100; _lmk04816_regs.PLL1_R_27 = 5; - _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_100UA; + _lmk04816_regs.PLL1_CP_GAIN_27 = lmk04816_regs_t::PLL1_CP_GAIN_27_1600UA; // PLL2 - 96 MHz compare frequency _lmk04816_regs.PLL2_N_30 = 5; |