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author | Josh Blum <josh@joshknows.com> | 2012-03-05 19:15:22 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2012-03-23 14:36:56 -0700 |
commit | 08e2432cdeeabd7010252b4a747a385e1b189614 (patch) | |
tree | 835fffb297188cfa6b20282e356e96df0377e5b1 /host/lib/usrp | |
parent | ee04c245f142ae6637091076445d955108d4da62 (diff) | |
download | uhd-08e2432cdeeabd7010252b4a747a385e1b189614.tar.gz uhd-08e2432cdeeabd7010252b4a747a385e1b189614.tar.bz2 uhd-08e2432cdeeabd7010252b4a747a385e1b189614.zip |
spi: work on fw support for simple spi core
Diffstat (limited to 'host/lib/usrp')
-rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index e14798ecb..7fe83e709 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -36,10 +36,10 @@ // Setting register offsets //////////////////////////////////////////////////////////////////////// #define SR_MISC 0 // 7 regs -#define SR_SIMTIMER 8 // 2 +#define SR_USER_REGS 8 // 2 #define SR_TIME64 10 // 6 #define SR_BUF_POOL 16 // 4 -#define SR_USER_REGS 20 // 2 +#define SR_SPI_CORE 20 // 3 #define SR_RX_FRONT 24 // 5 #define SR_RX_CTRL0 32 // 9 #define SR_RX_DSP0 48 // 7 |