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| author | Ashish Chaudhari <ashish@ettus.com> | 2014-04-24 12:40:58 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2014-04-24 12:40:58 -0700 |
| commit | 4b4e493f976094115dad7809121a092e2ac31668 (patch) | |
| tree | 9eef93cca3bda2183059d2812f36c6c061c32958 /host/lib/usrp | |
| parent | 8f46b048818ba107126910159c76453cfb2025e2 (diff) | |
| download | uhd-4b4e493f976094115dad7809121a092e2ac31668.tar.gz uhd-4b4e493f976094115dad7809121a092e2ac31668.tar.bz2 uhd-4b4e493f976094115dad7809121a092e2ac31668.zip | |
x300: Added hardware flush mechanism to PCIe logic.
- Added DMA enabled states to DMA logic to allow for hardware data flushing during init.
- niusrprio_session will now check for FPGA busy before downloading
Diffstat (limited to 'host/lib/usrp')
| -rw-r--r-- | host/lib/usrp/x300/x300_regs.hpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp index fb1786deb..cf1e33695 100644 --- a/host/lib/usrp/x300/x300_regs.hpp +++ b/host/lib/usrp/x300/x300_regs.hpp @@ -124,9 +124,12 @@ static const uint32_t FPGA_PCIE_SIG_REG = PCIE_FPGA_REG(0x0000); static const uint32_t FPGA_CNTR_LO_REG = PCIE_FPGA_REG(0x0004); static const uint32_t FPGA_CNTR_HI_REG = PCIE_FPGA_REG(0x0008); static const uint32_t FPGA_CNTR_FREQ_REG = PCIE_FPGA_REG(0x000C); +static const uint32_t FPGA_STATUS_REG = PCIE_FPGA_REG(0x0020); static const uint32_t FPGA_USR_SIG_REG_BASE = PCIE_FPGA_REG(0x0030); static const uint32_t FPGA_USR_SIG_REG_SIZE = 16; +static const uint32_t FPGA_STATUS_DMA_ACTIVE_MASK = 0x3F3F0000; + static const uint32_t PCIE_TX_DMA_REG_BASE = PCIE_FPGA_REG(0x0200); static const uint32_t PCIE_RX_DMA_REG_BASE = PCIE_FPGA_REG(0x0400); @@ -139,12 +142,15 @@ static const uint32_t DMA_PKT_COUNT_REG = 0xC; #define PCIE_TX_DMA_REG(REG, CHAN) (PCIE_TX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG) #define PCIE_RX_DMA_REG(REG, CHAN) (PCIE_RX_DMA_REG_BASE + (CHAN*DMA_REG_GRP_SIZE) + REG) -static const uint32_t DMA_CTRL_RESET = 1; +static const uint32_t DMA_CTRL_DISABLED = 0x00000000; +static const uint32_t DMA_CTRL_ENABLED = 0x00000002; +static const uint32_t DMA_CTRL_CLEAR_STB = 0x00000001; static const uint32_t DMA_CTRL_SW_BUF_U64 = (3 << 4); static const uint32_t DMA_CTRL_SW_BUF_U32 = (2 << 4); static const uint32_t DMA_CTRL_SW_BUF_U16 = (1 << 4); static const uint32_t DMA_CTRL_SW_BUF_U8 = (0 << 4); -static const uint32_t DMA_STATUS_ERROR = 1; +static const uint32_t DMA_STATUS_ERROR = 0x00000001; +static const uint32_t DMA_STATUS_BUSY = 0x00000002; static const uint32_t PCIE_ROUTER_REG_BASE = PCIE_FPGA_REG(0x0500); #define PCIE_ROUTER_REG(X) (PCIE_ROUTER_REG_BASE + X) |