Moved dsp (rx and tx), time config, and clock config (mostly) into the host.

6 files changed, 231 insertions, 143 deletions

diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp
index fd72aeaa4..86ee52594 100644
--- a/host/lib/usrp/usrp2/dboard_impl.cpp
+++ b/host/lib/usrp/usrp2/dboard_impl.cpp
@@ -15,10 +15,12 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+
+#include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
 #include <uhd/utils/assert.hpp>
-#include <uhd/types/clock_config.hpp>
 #include <boost/format.hpp>
-#include "usrp2_impl.hpp"
+#include <cstddef>
 
 using namespace uhd;
 using namespace uhd::usrp;
@@ -57,11 +59,13 @@ void usrp2_impl::dboard_init(void){
 
     //init the subdevs in use (use the first subdevice)
     _rx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0));
+    update_rx_mux_config();
+
     _tx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0));
-    update_mux_config();
+    update_tx_mux_config();
 }
 
-void usrp2_impl::update_mux_config(void){
+void usrp2_impl::update_rx_mux_config(void){
     //calculate the rx mux
     boost::uint32_t rx_mux = 0;
     ASSERT_THROW(_rx_subdevs_in_use.size() == 1);
@@ -76,6 +80,10 @@ void usrp2_impl::update_mux_config(void){
         rx_mux = (((rx_mux >> 0) & 0x3) << 2) | (((rx_mux >> 2) & 0x3) << 0);
     }
 
+    this->poke(offsetof(dsp_rx_regs_t, rx_mux) + DSP_RX_BASE, rx_mux);
+}
+
+void usrp2_impl::update_tx_mux_config(void){
     //calculate the tx mux
     boost::uint32_t tx_mux = 0x10;
     ASSERT_THROW(_tx_subdevs_in_use.size() == 1);
@@ -85,15 +93,7 @@ void usrp2_impl::update_mux_config(void){
         tx_mux = (((tx_mux >> 0) & 0x1) << 1) | (((tx_mux >> 1) & 0x1) << 0);
     }
 
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO);
-    out_data.data.mux_args.rx_mux = htonl(rx_mux);
-    out_data.data.mux_args.tx_mux = htonl(tx_mux);
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE);
+    this->poke(offsetof(dsp_tx_regs_t, tx_mux) + DSP_TX_BASE, tx_mux);
 }
 
 /***********************************************************************
@@ -129,7 +129,7 @@ void usrp2_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
 void usrp2_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){
     if (key.as<dboard_prop_t>() == DBOARD_PROP_USED_SUBDEVS){
         _rx_subdevs_in_use = val.as<prop_names_t>();
-        update_mux_config(); //if the val is bad, this will throw
+        update_rx_mux_config(); //if the val is bad, this will throw
         return;
     }
 
@@ -169,7 +169,7 @@ void usrp2_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
 void usrp2_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){
     if (key.as<dboard_prop_t>() == DBOARD_PROP_USED_SUBDEVS){
         _tx_subdevs_in_use = val.as<prop_names_t>();
-        update_mux_config(); //if the val is bad, this will throw
+        update_tx_mux_config(); //if the val is bad, this will throw
         return;
     }
 
diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp
index 0d43fac0e..6edfec61a 100644
--- a/host/lib/usrp/usrp2/dsp_impl.cpp
+++ b/host/lib/usrp/usrp2/dsp_impl.cpp
@@ -15,11 +15,13 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+#include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
 #include <uhd/utils/assert.hpp>
 #include <boost/format.hpp>
 #include <boost/assign/list_of.hpp>
 #include <boost/math/special_functions/round.hpp>
-#include "usrp2_impl.hpp"
+#include <cstddef>
 
 using namespace uhd;
 
@@ -64,25 +66,25 @@ void usrp2_impl::init_ddc_config(void){
     update_ddc_config();
 
     //initial command that kills streaming (in case if was left on)
-    //issue_ddc_stream_cmd(TODO)
+    stream_cmd_t stream_cmd_off;
+    stream_cmd_off.stream_now = true;
+    stream_cmd_off.continuous = false;
+    stream_cmd_off.num_samps = 0;
+    issue_ddc_stream_cmd(stream_cmd_off);
 }
 
 void usrp2_impl::update_ddc_config(void){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO);
-    out_data.data.ddc_args.freq_word = htonl(
-        calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq())
+    //set the decimation
+    this->poke(
+        offsetof(dsp_rx_regs_t, decim_rate) + DSP_RX_BASE, _ddc_decim
     );
-    out_data.data.ddc_args.decim = htonl(_ddc_decim);
+
+    //set the scaling
     static const boost::int16_t default_rx_scale_iq = 1024;
-    out_data.data.ddc_args.scale_iq = htonl(
+    this->poke(
+        offsetof(dsp_rx_regs_t, scale_iq) + DSP_RX_BASE,
         calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
     );
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE);
 }
 
 void usrp2_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
@@ -172,7 +174,10 @@ void usrp2_impl::ddc_set(const wax::obj &key, const wax::obj &val){
         ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0);
         ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0);
         _ddc_freq = new_freq; //shadow
-        update_ddc_config();
+        this->poke( //set the cordic
+            offsetof(dsp_rx_regs_t, freq) + DSP_RX_BASE,
+            calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq())
+        );
         return;
     }
     else if (key_name == "stream_cmd"){
@@ -210,20 +215,16 @@ void usrp2_impl::update_duc_config(void){
     double interp_cubed = std::pow(double(tmp_interp), 3);
     boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed));
 
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO);
-    out_data.data.duc_args.freq_word = htonl(
-        calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq())
+    //set the interpolation
+    this->poke(
+        offsetof(dsp_tx_regs_t, interp_rate) + DSP_TX_BASE, _ddc_decim
     );
-    out_data.data.duc_args.interp = htonl(_duc_interp);
-    out_data.data.duc_args.scale_iq = htonl(
+
+    //set the scaling
+    this->poke(
+        offsetof(dsp_tx_regs_t, scale_iq) + DSP_TX_BASE,
         calculate_iq_scale_word(scale, scale)
     );
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE);
 }
 
 /***********************************************************************
@@ -297,7 +298,10 @@ void usrp2_impl::duc_set(const wax::obj &key, const wax::obj &val){
         ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0);
         ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0);
         _duc_freq = new_freq; //shadow
-        update_duc_config();
+        this->poke( //set the cordic
+            offsetof(dsp_tx_regs_t, freq) + DSP_TX_BASE,
+            calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq())
+        );
         return;
     }
 
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index 565154305..c168614ee 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -60,9 +60,6 @@ typedef enum{
     USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO = 'd',
     USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE = 'D',
 
-    USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO = 'c',
-    USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE = 'C',
-
     USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO = 's',
     USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE = 'S',
 
@@ -78,21 +75,9 @@ typedef enum{
     USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO = 'y',
     USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE = 'Y',
 
-    USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO = '\\',
-    USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE = '/',
-
     USRP2_CTRL_ID_SEND_STREAM_COMMAND_FOR_ME_BRO = '{',
     USRP2_CTRL_ID_GOT_THAT_STREAM_COMMAND_DUDE = '}',
 
-    USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO = '\'',
-    USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE = '"',
-
-    USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO = '<',
-    USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE = '>',
-
-    USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO = '-',
-    USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE = '_',
-
     USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO = 'p',
     USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE = 'P',
 
@@ -104,22 +89,6 @@ typedef enum{
 } usrp2_ctrl_id_t;
 
 typedef enum{
-    USRP2_PPS_SOURCE_SMA,
-    USRP2_PPS_SOURCE_MIMO
-} usrp2_pps_source_t;
-
-typedef enum{
-    USRP2_PPS_POLARITY_POS,
-    USRP2_PPS_POLARITY_NEG
-} usrp2_pps_polarity_t;
-
-typedef enum{
-    USRP2_REF_SOURCE_INT,
-    USRP2_REF_SOURCE_SMA,
-    USRP2_REF_SOURCE_MIMO
-} usrp2_ref_source_t;
-
-typedef enum{
     USRP2_DIR_RX,
     USRP2_DIR_TX
 } usrp2_dir_which_t;
@@ -140,12 +109,6 @@ typedef struct{
             _SINS_ uint16_t tx_id;
         } dboard_ids;
         struct {
-            _SINS_ uint8_t pps_source;
-            _SINS_ uint8_t pps_polarity;
-            _SINS_ uint8_t ref_source;
-            _SINS_ uint8_t _pad;
-        } clock_config;
-        struct {
             _SINS_ uint8_t dev;
             _SINS_ uint8_t edge;
             _SINS_ uint8_t readback;
@@ -164,11 +127,6 @@ typedef struct{
             _SINS_ uint32_t value;
         } aux_args;
         struct {
-            _SINS_ uint32_t freq_word;
-            _SINS_ uint32_t decim;
-            _SINS_ uint32_t scale_iq;
-        } ddc_args;
-        struct {
             _SINS_ uint8_t now; //stream now?
             _SINS_ uint8_t continuous; //auto-reload commmands?
             _SINS_ uint8_t _pad[2];
@@ -177,20 +135,6 @@ typedef struct{
             _SINS_ uint32_t num_samps;
         } stream_cmd;
         struct {
-            _SINS_ uint32_t freq_word;
-            _SINS_ uint32_t interp;
-            _SINS_ uint32_t scale_iq;
-        } duc_args;
-        struct {
-            _SINS_ uint32_t secs;
-            _SINS_ uint32_t ticks;
-            _SINS_ uint8_t now;
-        } time_args;
-        struct {
-            _SINS_ uint32_t rx_mux;
-            _SINS_ uint32_t tx_mux;
-        } mux_args;
-        struct {
             _SINS_ uint32_t addr;
             _SINS_ uint32_t data;
         } poke_args;
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 35dfd6287..eff53c5b2 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -15,9 +15,12 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
+#include "usrp2_impl.hpp"
+#include "usrp2_regs.hpp"
 #include <uhd/utils/assert.hpp>
 #include <uhd/types/mac_addr.hpp>
-#include "usrp2_impl.hpp"
+#include <uhd/types/dict.hpp>
+#include <cstddef>
 
 using namespace uhd;
 
@@ -46,55 +49,36 @@ void usrp2_impl::init_clock_config(void){
 }
 
 void usrp2_impl::update_clock_config(void){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO);
-
-    //translate ref source enums
-    switch(_clock_config.ref_source){
-    case clock_config_t::REF_INT:
-        out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_INT; break;
-    case clock_config_t::REF_SMA:
-        out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_SMA; break;
-    case clock_config_t::REF_MIMO:
-        out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_MIMO; break;
-    default: throw std::runtime_error("usrp2: unhandled clock configuration ref source");
-    }
+    boost::uint32_t pps_flags = 0;
 
     //translate pps source enums
     switch(_clock_config.pps_source){
-    case clock_config_t::PPS_SMA:
-        out_data.data.clock_config.pps_source = USRP2_PPS_SOURCE_SMA; break;
-    case clock_config_t::PPS_MIMO:
-        out_data.data.clock_config.pps_source = USRP2_PPS_SOURCE_MIMO; break;
+    case clock_config_t::PPS_SMA:  pps_flags |= PPS_FLAG_SMA;  break;
+    case clock_config_t::PPS_MIMO: pps_flags |= PPS_FLAG_MIMO; break;
     default: throw std::runtime_error("usrp2: unhandled clock configuration pps source");
     }
 
     //translate pps polarity enums
     switch(_clock_config.pps_polarity){
-    case clock_config_t::PPS_POS:
-        out_data.data.clock_config.pps_source = USRP2_PPS_POLARITY_POS; break;
-    case clock_config_t::PPS_NEG:
-        out_data.data.clock_config.pps_source = USRP2_PPS_POLARITY_NEG; break;
+    case clock_config_t::PPS_POS: pps_flags |= PPS_FLAG_POSEDGE; break;
+    case clock_config_t::PPS_NEG: pps_flags |= PPS_FLAG_NEGEDGE; break;
     default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity");
     }
 
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE);
+    //set the pps flags
+    this->poke(offsetof(sr_time64_t, flags) + TIME64_BASE, pps_flags);
+
+    //TODO clock source ref 10mhz (spi ad9510)
 }
 
 void usrp2_impl::set_time_spec(const time_spec_t &time_spec, bool now){
-    //setup the out data
-    usrp2_ctrl_data_t out_data;
-    out_data.id = htonl(USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO);
-    out_data.data.time_args.secs  = htonl(time_spec.secs);
-    out_data.data.time_args.ticks = htonl(time_spec.ticks);
-    out_data.data.time_args.now   = (now)? 1 : 0;
-
-    //send and recv
-    usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data);
-    ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE);
+    //set ticks and seconds
+    this->poke(offsetof(sr_time64_t, secs) + TIME64_BASE, time_spec.secs);
+    this->poke(offsetof(sr_time64_t, ticks) + TIME64_BASE, time_spec.ticks);
+
+    //set the register to latch it all in
+    boost::uint32_t imm_flags = (now)? TIME64_LATCH_NOW : TIME64_LATCH_NEXT_PPS;
+    this->poke(offsetof(sr_time64_t, imm) + TIME64_BASE, imm_flags);
 }
 
 /***********************************************************************
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index 1b6175195..55be420cd 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -172,7 +172,8 @@ private:
     void tx_dboard_set(const wax::obj &, const wax::obj &);
     uhd::dict<std::string, wax_obj_proxy::sptr> _tx_dboards;
     uhd::prop_names_t _tx_subdevs_in_use;
-    void update_mux_config(void);
+    void update_rx_mux_config(void);
+    void update_tx_mux_config(void);
 
     //methods and shadows for the ddc dsp
     std::vector<size_t> _allowed_decim_and_interp_rates;
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 9cf0b1fbc..7d868c264 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -20,6 +20,161 @@
 
 #include <boost/cstdint.hpp>
 
+////////////////////////////////////////////////////
+// Settings Bus, Slave #7, Not Byte Addressable!
+//
+// Output-only from processor point-of-view.
+// 1KB of address space (== 256 32-bit write-only regs)
+
+
+#define MISC_OUTPUT_BASE        0xD400
+#define TX_PROTOCOL_ENGINE_BASE 0xD480
+#define RX_PROTOCOL_ENGINE_BASE 0xD4C0
+#define BUFFER_POOL_CTRL_BASE   0xD500
+#define LAST_SETTING_REG        0xD7FC  // last valid setting register
+
+#define SR_MISC 0
+#define SR_TX_PROT_ENG 32
+#define SR_RX_PROT_ENG 48
+#define SR_BUFFER_POOL_CTRL 64
+#define SR_UDP_SM 96
+#define SR_TX_DSP 208
+#define SR_TX_CTRL 224
+#define SR_RX_DSP 160
+#define SR_RX_CTRL 176
+#define SR_TIME64 192
+#define SR_SIMTIMER 198
+#define SR_LAST 255
+
+#define _SR_ADDR(sr)    (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t))
+
+/////////////////////////////////////////////////
+// VITA49 64 bit time (write only)
+////////////////////////////////////////////////
+
+#define TIME64_BASE _SR_ADDR(SR_TIME64)
+
+  /*!
+   * \brief Time 64 flags
+   *
+   * <pre>
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   * </pre>
+   */
+typedef struct {
+    boost::uint32_t secs;   // value to set absolute secs to on next PPS
+    boost::uint32_t ticks;  // value to set absolute ticks to on next PPS
+    boost::uint32_t flags;  // flags - see chart above
+    boost::uint32_t imm;    // set immediate (0=latch on next pps, 1=latch immediate, default=0)
+} sr_time64_t;
+
+//pps flags (see above)
+#define PPS_FLAG_NEGEDGE (0 << 0)
+#define PPS_FLAG_POSEDGE (1 << 0)
+#define PPS_FLAG_SMA     (0 << 1)
+#define PPS_FLAG_MIMO    (1 << 1)
+
+#define TIME64_LATCH_NOW 1
+#define TIME64_LATCH_NEXT_PPS 0
+
+/////////////////////////////////////////////////
+// DSP TX Regs
+////////////////////////////////////////////////
+
+#define DSP_TX_BASE _SR_ADDR(SR_TX_DSP)
+
+typedef struct {
+    boost::int32_t      freq;
+    boost::uint32_t     scale_iq;       // {scale_i,scale_q}
+    boost::uint32_t     interp_rate;
+    boost::uint32_t     _padding0;      // padding for the tx_mux
+                                        //   NOT freq, scale, interp
+  /*!
+   * \brief output mux configuration.
+   *
+   * <pre>
+   *     3                   2                   1                       
+   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   *  +-------------------------------+-------+-------+-------+-------+
+   *  |                                               | DAC1  |  DAC0 |
+   *  +-------------------------------+-------+-------+-------+-------+
+   * 
+   *  There are N DUCs (1 now) with complex inputs and outputs.
+   *  There are two DACs.
+   * 
+   *  Each 4-bit DACx field specifies the source for the DAC
+   *  Each subfield is coded like this: 
+   * 
+   *     3 2 1 0
+   *    +-------+
+   *    |   N   |
+   *    +-------+
+   * 
+   *  N specifies which DUC output is connected to this DAC.
+   * 
+   *   N   which interp output
+   *  ---  -------------------
+   *   0   DUC 0 I
+   *   1   DUC 0 Q
+   *   2   DUC 1 I
+   *   3   DUC 1 Q
+   *   F   All Zeros
+   *   
+   * The default value is 0x10
+   * </pre>
+   */
+    boost::uint32_t tx_mux;
+
+} dsp_tx_regs_t;
+
+/////////////////////////////////////////////////
+// DSP RX Regs
+////////////////////////////////////////////////
+
+#define DSP_RX_BASE _SR_ADDR(SR_RX_DSP)
+
+typedef struct {
+    boost::int32_t      freq;
+    boost::uint32_t     scale_iq;       // {scale_i,scale_q}
+    boost::uint32_t     decim_rate;
+    boost::uint32_t     dcoffset_i;     // Bit 31 high sets fixed offset mode, using lower 14 bits,
+                                        // otherwise it is automatic 
+    boost::uint32_t     dcoffset_q;     // Bit 31 high sets fixed offset mode, using lower 14 bits
+
+  /*!
+   * \brief input mux configuration.
+   *
+   * This determines which ADC (or constant zero) is connected to 
+   * each DDC input.  There are N DDCs (1 now).  Each has two inputs.
+   *
+   * <pre>
+   * Mux value:
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   * |                                                       |Q0 |I0 |
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   *
+   * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   *
+   * The default value is 0x4
+   * </pre>
+   */
+    boost::uint32_t     rx_mux;        // called adc_mux in dsp_core_rx.v
+
+} dsp_rx_regs_t;
+
 ////////////////////////////////////////////////
 // GPIO, Slave 4
 //
@@ -35,10 +190,10 @@ typedef struct {
 } gpio_regs_t;
 
 // each 2-bit sel field is layed out this way
-#define GPIO_SEL_SW	   0 // if pin is an output, set by software in the io reg
-#define	GPIO_SEL_ATR	   1 // if pin is an output, set by ATR logic
-#define	GPIO_SEL_DEBUG_0   2 // if pin is an output, debug lines from FPGA fabric
-#define	GPIO_SEL_DEBUG_1   3 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_SW        0 // if pin is an output, set by software in the io reg
+#define GPIO_SEL_ATR       1 // if pin is an output, set by ATR logic
+#define GPIO_SEL_DEBUG_0   2 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_DEBUG_1   3 // if pin is an output, debug lines from FPGA fabric
 
 ///////////////////////////////////////////////////
 // ATR Controller, Slave 11
@@ -46,12 +201,12 @@ typedef struct {
 #define ATR_BASE  0xE400
 
 typedef struct {
-    boost::uint32_t	v[16];
+    boost::uint32_t v[16];
 } atr_regs_t;
 
-#define	ATR_IDLE	0x0	// indicies into v
-#define ATR_TX		0x1
-#define	ATR_RX		0x2
-#define	ATR_FULL	0x3
+#define ATR_IDLE    0x0 // indicies into v
+#define ATR_TX      0x1
+#define ATR_RX      0x2
+#define ATR_FULL    0x3
 
 #endif /* INCLUDED_USRP2_REGS_HPP */