Merge branch 'maint'

15 files changed, 182 insertions, 181 deletions

diff --git a/host/lib/usrp/x300/x300_adc_ctrl.cpp b/host/lib/usrp/x300/x300_adc_ctrl.cpp
index ce6102b35..fed2ffaf7 100644
--- a/host/lib/usrp/x300/x300_adc_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_adc_ctrl.cpp
@@ -97,7 +97,7 @@ public:
         return gain_bits/2;
     }
 
-    void set_test_word(const std::string &patterna, const std::string &patternb, const boost::uint32_t num)
+    void set_test_word(const std::string &patterna, const std::string &patternb, const uint32_t num)
     {
         _ads62p48_regs.custom_pattern_low = num & 0xff;
         _ads62p48_regs.custom_pattern_high = num >> 8;
@@ -131,9 +131,9 @@ private:
     uhd::spi_iface::sptr _iface;
     const size_t _slaveno;
 
-    void send_ads62p48_reg(boost::uint8_t addr)
+    void send_ads62p48_reg(uint8_t addr)
     {
-        boost::uint16_t reg = _ads62p48_regs.get_write_reg(addr);
+        uint16_t reg = _ads62p48_regs.get_write_reg(addr);
         _iface->write_spi(_slaveno, spi_config_t::EDGE_FALL, reg, 16);
     }
 };
diff --git a/host/lib/usrp/x300/x300_adc_ctrl.hpp b/host/lib/usrp/x300/x300_adc_ctrl.hpp
index 90fb88cec..bda93628e 100644
--- a/host/lib/usrp/x300/x300_adc_ctrl.hpp
+++ b/host/lib/usrp/x300/x300_adc_ctrl.hpp
@@ -39,7 +39,7 @@ public:
 
     virtual double set_gain(const double &) = 0;
 
-    virtual void set_test_word(const std::string &patterna, const std::string &patternb, const boost::uint32_t = 0) = 0;
+    virtual void set_test_word(const std::string &patterna, const std::string &patternb, const uint32_t = 0) = 0;
 
     virtual void reset(void) = 0;
 };
diff --git a/host/lib/usrp/x300/x300_adc_dac_utils.cpp b/host/lib/usrp/x300/x300_adc_dac_utils.cpp
index cd337febb..6fd0ca50b 100644
--- a/host/lib/usrp/x300/x300_adc_dac_utils.cpp
+++ b/host/lib/usrp/x300/x300_adc_dac_utils.cpp
@@ -47,7 +47,7 @@ void x300_impl::synchronize_dacs(const std::vector<radio_perifs_t*>& radios)
         boost::posix_time::microsec_clock::local_time() - t_start;
 
     //Add 100% of headroom + uncertaintly to the command time
-    boost::uint64_t t_sync_us = (t_elapsed.total_microseconds() * 2) + 13000 /*Scheduler latency*/;
+    uint64_t t_sync_us = (t_elapsed.total_microseconds() * 2) + 13000 /*Scheduler latency*/;
 
     //Pick radios[0] as the time reference.
     uhd::time_spec_t sync_time =
@@ -71,9 +71,9 @@ void x300_impl::synchronize_dacs(const std::vector<radio_perifs_t*>& radios)
  * ADC: Self-test operations
  **********************************************************************/
 
-static void check_adc(uhd::wb_iface::sptr iface, const boost::uint32_t val, const boost::uint32_t i)
+static void check_adc(uhd::wb_iface::sptr iface, const uint32_t val, const uint32_t i)
 {
-    boost::uint32_t adc_rb = iface->peek32(uhd::usrp::radio::RB32_RX);
+    uint32_t adc_rb = iface->peek32(uhd::usrp::radio::RB32_RX);
     adc_rb ^= 0xfffc0000; //adapt for I inversion in FPGA
     if (val != adc_rb) {
         throw uhd::runtime_error(
@@ -81,7 +81,7 @@ static void check_adc(uhd::wb_iface::sptr iface, const boost::uint32_t val, cons
     }
 }
 
-void x300_impl::self_test_adcs(mboard_members_t& mb, boost::uint32_t ramp_time_ms) {
+void x300_impl::self_test_adcs(mboard_members_t& mb, uint32_t ramp_time_ms) {
     for (size_t r = 0; r < mboard_members_t::NUM_RADIOS; r++) {
         radio_perifs_t &perif = mb.radio_perifs[r];
 
@@ -186,20 +186,20 @@ void x300_impl::self_cal_adc_capture_delay(mboard_members_t& mb, const size_t ra
     radio_perifs_t& perif = mb.radio_perifs[radio_i];
     if (print_status) UHD_MSG(status) << "Running ADC capture delay self-cal..." << std::flush;
 
-    static const boost::uint32_t NUM_DELAY_STEPS = 32;   //The IDELAYE2 element has 32 steps
-    static const boost::uint32_t NUM_RETRIES     = 2;    //Retry self-cal if it fails in warmup situations
-    static const boost::int32_t  MIN_WINDOW_LEN  = 4;
+    static const uint32_t NUM_DELAY_STEPS = 32;   //The IDELAYE2 element has 32 steps
+    static const uint32_t NUM_RETRIES     = 2;    //Retry self-cal if it fails in warmup situations
+    static const int32_t  MIN_WINDOW_LEN  = 4;
 
-    boost::int32_t win_start = -1, win_stop = -1;
-    boost::uint32_t iter = 0;
+    int32_t win_start = -1, win_stop = -1;
+    uint32_t iter = 0;
     while (iter++ < NUM_RETRIES) {
-        for (boost::uint32_t dly_tap = 0; dly_tap < NUM_DELAY_STEPS; dly_tap++) {
+        for (uint32_t dly_tap = 0; dly_tap < NUM_DELAY_STEPS; dly_tap++) {
             //Apply delay
             perif.regmap->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_VAL, dly_tap);
             perif.regmap->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 1);
             perif.regmap->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 0);
 
-            boost::uint32_t err_code = 0;
+            uint32_t err_code = 0;
 
             // -- Test I Channel --
             //Put ADC in ramp test mode. Tie the other channel to all ones.
@@ -270,7 +270,7 @@ void x300_impl::self_cal_adc_capture_delay(mboard_members_t& mb, const size_t ra
         throw uhd::runtime_error("self_cal_adc_capture_delay: Self calibration failed. Valid window too narrow.");
     }
 
-    boost::uint32_t ideal_tap = (win_stop + win_start) / 2;
+    uint32_t ideal_tap = (win_stop + win_start) / 2;
     perif.regmap->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_VAL, ideal_tap);
     perif.regmap->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 1);
     perif.regmap->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 0);
@@ -304,7 +304,7 @@ double x300_impl::self_cal_adc_xfer_delay(mboard_members_t& mb, bool apply_delay
         double delay = mb.clock->set_clock_delay(X300_CLOCK_WHICH_ADC0, delay_incr*i + delay_start);
         wait_for_clk_locked(mb, fw_regmap_t::clk_status_reg_t::LMK_LOCK, 0.1);
 
-        boost::uint32_t err_code = 0;
+        uint32_t err_code = 0;
         for (size_t r = 0; r < mboard_members_t::NUM_RADIOS; r++) {
             //Test each channel (I and Q) individually so as to not accidentally trigger
             //on the data from the other channel if there is a swap
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp
index 3df2b7c02..b8b100ceb 100644
--- a/host/lib/usrp/x300/x300_clock_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp
@@ -19,7 +19,7 @@
 #include "x300_clock_ctrl.hpp"
 #include <uhd/utils/safe_call.hpp>
 #include <uhd/utils/math.hpp>
-#include <boost/cstdint.hpp>
+#include <stdint.h>
 #include <boost/format.hpp>
 #include <boost/math/special_functions/round.hpp>
 #include <stdexcept>
@@ -27,7 +27,7 @@
 #include <cstdlib>
 
 static const double X300_REF_CLK_OUT_RATE  = 10e6;
-static const boost::uint16_t X300_MAX_CLKOUT_DIV = 1045;
+static const uint16_t X300_MAX_CLKOUT_DIV = 1045;
 
 struct x300_clk_delays {
     x300_clk_delays() :
@@ -118,9 +118,9 @@ public:
     }
 
     void set_dboard_rate(const x300_clock_which_t which, double rate) {
-        boost::uint16_t div = boost::uint16_t(_vco_freq / rate);
-        boost::uint16_t *reg = NULL;
-        boost::uint8_t addr = 0xFF;
+        uint16_t div = uint16_t(_vco_freq / rate);
+        uint16_t *reg = NULL;
+        uint8_t addr = 0xFF;
 
         // Make sure requested rate is an even divisor of the VCO frequency
         if (not math::frequencies_are_equal(_vco_freq / div, rate))
@@ -234,16 +234,16 @@ public:
         this->write_regs(8);
     }
 
-    void write_regs(boost::uint8_t addr) {
-        boost::uint32_t data = _lmk04816_regs.get_reg(addr);
+    void write_regs(uint8_t addr) {
+        uint32_t data = _lmk04816_regs.get_reg(addr);
         _spiface->write_spi(_slaveno, spi_config_t::EDGE_RISE, data,32);
     }
 
     double set_clock_delay(const x300_clock_which_t which, const double delay_ns, const bool resync = true) {
         //All dividers have are delayed by 5 taps by default. The delay
         //set by this function is relative to the 5 tap delay
-        static const boost::uint16_t DDLY_MIN_TAPS  = 5;
-        static const boost::uint16_t DDLY_MAX_TAPS  = 522;  //Extended mode
+        static const uint16_t DDLY_MIN_TAPS  = 5;
+        static const uint16_t DDLY_MAX_TAPS  = 522;  //Extended mode
 
         //The resolution and range of the analog delay is fixed
         static const double ADLY_RES_NS = 0.025;
@@ -259,19 +259,19 @@ public:
         //A caveat here is that the analog delay starts at ADLY_MIN_NS, so we need to back off
         //by that much when coming up with the digital taps so that the difference can be made
         //up using the analog delay.
-        boost::uint16_t ddly_taps = 0;
+        uint16_t ddly_taps = 0;
         if (delay_ns < ADLY_MIN_NS) {
-            ddly_taps = static_cast<boost::uint16_t>(std::floor((delay_ns)/vco_period_ns));
+            ddly_taps = static_cast<uint16_t>(std::floor((delay_ns)/vco_period_ns));
         } else {
-            ddly_taps = static_cast<boost::uint16_t>(std::floor((delay_ns-ADLY_MIN_NS)/vco_period_ns));
+            ddly_taps = static_cast<uint16_t>(std::floor((delay_ns-ADLY_MIN_NS)/vco_period_ns));
         }
         double leftover_delay = delay_ns - (vco_period_ns * ddly_taps);
 
         //Compute settings
-        boost::uint16_t ddly_value    = ddly_taps + DDLY_MIN_TAPS;
+        uint16_t ddly_value    = ddly_taps + DDLY_MIN_TAPS;
         bool            adly_en       = false;
-        boost::uint8_t  adly_value    = 0;
-        boost::uint8_t  half_shift_en = 0;
+        uint8_t  adly_value    = 0;
+        uint8_t  half_shift_en = 0;
 
         if (ddly_value > DDLY_MAX_TAPS) {
             throw uhd::value_error("set_clock_delay: Requested delay is out of range.");
@@ -282,18 +282,18 @@ public:
             //The VCO is running too slowly for us to compensate the digital delay difference using
             //analog delay. Do the best we can.
             adly_en = true;
-            adly_value = static_cast<boost::uint8_t>(boost::math::round((ADLY_MAX_NS-ADLY_MIN_NS)/ADLY_RES_NS));
+            adly_value = static_cast<uint8_t>(boost::math::round((ADLY_MAX_NS-ADLY_MIN_NS)/ADLY_RES_NS));
             coerced_delay += ADLY_MAX_NS;
         } else if (leftover_delay >= ADLY_MIN_NS && leftover_delay <= ADLY_MAX_NS) {
             //The leftover delay can be compensated by the analog delay up to the analog delay resolution
             adly_en = true;
-            adly_value = static_cast<boost::uint8_t>(boost::math::round((leftover_delay-ADLY_MIN_NS)/ADLY_RES_NS));
+            adly_value = static_cast<uint8_t>(boost::math::round((leftover_delay-ADLY_MIN_NS)/ADLY_RES_NS));
             coerced_delay += ADLY_MIN_NS+(ADLY_RES_NS*adly_value);
         } else if (leftover_delay >= (ADLY_MIN_NS - half_vco_period_ns) && leftover_delay < ADLY_MIN_NS) {
             //The leftover delay if less than the minimum supported analog delay but if we move the digital
             //delay back by half a VCO cycle then it will be in the range of the analog delay. So do that!
             adly_en = true;
-            adly_value = static_cast<boost::uint8_t>(boost::math::round((leftover_delay+half_vco_period_ns-ADLY_MIN_NS)/ADLY_RES_NS));
+            adly_value = static_cast<uint8_t>(boost::math::round((leftover_delay+half_vco_period_ns-ADLY_MIN_NS)/ADLY_RES_NS));
             half_shift_en = 1;
             coerced_delay += ADLY_MIN_NS+(ADLY_RES_NS*adly_value)-half_vco_period_ns;
         } else {
@@ -600,10 +600,10 @@ private:
                 break;
         };
 
-        boost::uint16_t master_clock_div = static_cast<boost::uint16_t>(
+        uint16_t master_clock_div = static_cast<uint16_t>(
             std::ceil(_vco_freq / _master_clock_rate));
 
-        boost::uint16_t dboard_div = static_cast<boost::uint16_t>(
+        uint16_t dboard_div = static_cast<uint16_t>(
             std::ceil(_vco_freq / _dboard_clock_rate));
 
         /* Reset the LMK clock controller. */
@@ -632,7 +632,7 @@ private:
         // Register 5
         _lmk04816_regs.CLKout10_11_PD = lmk04816_regs_t::CLKOUT10_11_PD_NORMAL;
         _lmk04816_regs.CLKout10_11_DIV =
-            static_cast<boost::uint16_t>(std::ceil(_vco_freq / _system_ref_rate));
+            static_cast<uint16_t>(std::ceil(_vco_freq / _system_ref_rate));
 
         // Register 6
         _lmk04816_regs.CLKout0_TYPE = lmk04816_regs_t::CLKOUT0_TYPE_LVDS; //FPGA
diff --git a/host/lib/usrp/x300/x300_dac_ctrl.cpp b/host/lib/usrp/x300/x300_dac_ctrl.cpp
index 6ffd1ede4..162eeb143 100644
--- a/host/lib/usrp/x300/x300_dac_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_dac_ctrl.cpp
@@ -250,7 +250,7 @@ public:
 
     void _sleep_mode(bool sleep)
     {
-        boost::uint8_t sleep_val = sleep ? (1<<7) : 0x00;
+        uint8_t sleep_val = sleep ? (1<<7) : 0x00;
         //Set sleep word and default fullscale value
         write_ad9146_reg(0x41, sleep_val | 0x01);    //I DAC
         write_ad9146_reg(0x45, sleep_val | 0x01);    //Q DAC
diff --git a/host/lib/usrp/x300/x300_dboard_iface.cpp b/host/lib/usrp/x300/x300_dboard_iface.cpp
index b28768f90..092c888b0 100644
--- a/host/lib/usrp/x300/x300_dboard_iface.cpp
+++ b/host/lib/usrp/x300/x300_dboard_iface.cpp
@@ -126,47 +126,47 @@ double x300_dboard_iface::get_codec_rate(unit_t unit)
 /***********************************************************************
  * GPIO
  **********************************************************************/
-void x300_dboard_iface::set_pin_ctrl(unit_t unit, boost::uint32_t value, boost::uint32_t mask)
+void x300_dboard_iface::set_pin_ctrl(unit_t unit, uint32_t value, uint32_t mask)
 {
     _config.gpio->set_pin_ctrl(unit, value, mask);
 }
 
-boost::uint32_t x300_dboard_iface::get_pin_ctrl(unit_t unit)
+uint32_t x300_dboard_iface::get_pin_ctrl(unit_t unit)
 {
     return _config.gpio->get_pin_ctrl(unit);
 }
 
-void x300_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t reg, boost::uint32_t value, boost::uint32_t mask)
+void x300_dboard_iface::set_atr_reg(unit_t unit, atr_reg_t reg, uint32_t value, uint32_t mask)
 {
     _config.gpio->set_atr_reg(unit, reg, value, mask);
 }
 
-boost::uint32_t x300_dboard_iface::get_atr_reg(unit_t unit, atr_reg_t reg)
+uint32_t x300_dboard_iface::get_atr_reg(unit_t unit, atr_reg_t reg)
 {
     return _config.gpio->get_atr_reg(unit, reg);
 }
 
-void x300_dboard_iface::set_gpio_ddr(unit_t unit, boost::uint32_t value, boost::uint32_t mask)
+void x300_dboard_iface::set_gpio_ddr(unit_t unit, uint32_t value, uint32_t mask)
 {
     _config.gpio->set_gpio_ddr(unit, value, mask);
 }
 
-boost::uint32_t x300_dboard_iface::get_gpio_ddr(unit_t unit)
+uint32_t x300_dboard_iface::get_gpio_ddr(unit_t unit)
 {
     return _config.gpio->get_gpio_ddr(unit);
 }
 
-void x300_dboard_iface::set_gpio_out(unit_t unit, boost::uint32_t value, boost::uint32_t mask)
+void x300_dboard_iface::set_gpio_out(unit_t unit, uint32_t value, uint32_t mask)
 {
     _config.gpio->set_gpio_out(unit, value, mask);
 }
 
-boost::uint32_t x300_dboard_iface::get_gpio_out(unit_t unit)
+uint32_t x300_dboard_iface::get_gpio_out(unit_t unit)
 {
     return _config.gpio->get_gpio_out(unit);
 }
 
-boost::uint32_t x300_dboard_iface::read_gpio(unit_t unit)
+uint32_t x300_dboard_iface::read_gpio(unit_t unit)
 {
     return _config.gpio->read_gpio(unit);
 }
@@ -177,20 +177,20 @@ boost::uint32_t x300_dboard_iface::read_gpio(unit_t unit)
 void x300_dboard_iface::write_spi(
     unit_t unit,
     const spi_config_t &config,
-    boost::uint32_t data,
+    uint32_t data,
     size_t num_bits
 ){
-    boost::uint32_t slave = 0;
+    uint32_t slave = 0;
     if (unit == UNIT_TX) slave |= _config.tx_spi_slaveno;
     if (unit == UNIT_RX) slave |= _config.rx_spi_slaveno;
 
     _config.spi->write_spi(int(slave), config, data, num_bits);
 }
 
-boost::uint32_t x300_dboard_iface::read_write_spi(
+uint32_t x300_dboard_iface::read_write_spi(
     unit_t unit,
     const spi_config_t &config,
-    boost::uint32_t data,
+    uint32_t data,
     size_t num_bits
 ){
     if (unit == UNIT_BOTH) throw uhd::runtime_error("UNIT_BOTH not supported.");
@@ -202,12 +202,12 @@ boost::uint32_t x300_dboard_iface::read_write_spi(
 /***********************************************************************
  * I2C
  **********************************************************************/
-void x300_dboard_iface::write_i2c(boost::uint16_t addr, const byte_vector_t &bytes)
+void x300_dboard_iface::write_i2c(uint16_t addr, const byte_vector_t &bytes)
 {
     return _config.i2c->write_i2c(addr, bytes);
 }
 
-byte_vector_t x300_dboard_iface::read_i2c(boost::uint16_t addr, size_t num_bytes)
+byte_vector_t x300_dboard_iface::read_i2c(uint16_t addr, size_t num_bytes)
 {
     return _config.i2c->read_i2c(addr, num_bytes);
 }
@@ -280,7 +280,7 @@ double x300_dboard_iface::read_aux_adc(unit_t unit, aux_adc_t which)
         unit_to_spi_adc[unit], config,
         ad7922_regs.get_reg(), 16
     );
-    ad7922_regs.set_reg(boost::uint16_t(_config.spi->read_spi(
+    ad7922_regs.set_reg(uint16_t(_config.spi->read_spi(
         unit_to_spi_adc[unit], config,
         ad7922_regs.get_reg(), 16
     )));
diff --git a/host/lib/usrp/x300/x300_dboard_iface.hpp b/host/lib/usrp/x300/x300_dboard_iface.hpp
index 124d768e8..82e08b016 100644
--- a/host/lib/usrp/x300/x300_dboard_iface.hpp
+++ b/host/lib/usrp/x300/x300_dboard_iface.hpp
@@ -38,7 +38,7 @@ struct x300_dboard_iface_config_t
     x300_clock_ctrl::sptr                       clock;
     x300_clock_which_t                          which_rx_clk;
     x300_clock_which_t                          which_tx_clk;
-    boost::uint8_t                              dboard_slot;
+    uint8_t                              dboard_slot;
     uhd::timed_wb_iface::sptr                   cmd_time_ctrl;
 };
 
@@ -59,21 +59,21 @@ public:
     void write_aux_dac(unit_t, aux_dac_t, double);
     double read_aux_adc(unit_t, aux_adc_t);
 
-    void set_pin_ctrl(unit_t unit, boost::uint32_t value, boost::uint32_t mask = 0xffffffff);
-    boost::uint32_t get_pin_ctrl(unit_t unit);
-    void set_atr_reg(unit_t unit, atr_reg_t reg, boost::uint32_t value, boost::uint32_t mask = 0xffffffff);
-    boost::uint32_t get_atr_reg(unit_t unit, atr_reg_t reg);
-    void set_gpio_ddr(unit_t unit, boost::uint32_t value, boost::uint32_t mask = 0xffffffff);
-    boost::uint32_t get_gpio_ddr(unit_t unit);
-    void set_gpio_out(unit_t unit, boost::uint32_t value, boost::uint32_t mask = 0xffffffff);
-    boost::uint32_t get_gpio_out(unit_t unit);
-    boost::uint32_t read_gpio(unit_t unit);
+    void set_pin_ctrl(unit_t unit, uint32_t value, uint32_t mask = 0xffffffff);
+    uint32_t get_pin_ctrl(unit_t unit);
+    void set_atr_reg(unit_t unit, atr_reg_t reg, uint32_t value, uint32_t mask = 0xffffffff);
+    uint32_t get_atr_reg(unit_t unit, atr_reg_t reg);
+    void set_gpio_ddr(unit_t unit, uint32_t value, uint32_t mask = 0xffffffff);
+    uint32_t get_gpio_ddr(unit_t unit);
+    void set_gpio_out(unit_t unit, uint32_t value, uint32_t mask = 0xffffffff);
+    uint32_t get_gpio_out(unit_t unit);
+    uint32_t read_gpio(unit_t unit);
 
     void set_command_time(const uhd::time_spec_t& t);
     uhd::time_spec_t get_command_time(void);
 
-    void write_i2c(boost::uint16_t, const uhd::byte_vector_t &);
-    uhd::byte_vector_t read_i2c(boost::uint16_t, size_t);
+    void write_i2c(uint16_t, const uhd::byte_vector_t &);
+    uhd::byte_vector_t read_i2c(uint16_t, size_t);
 
     void set_clock_rate(unit_t, double);
     double get_clock_rate(unit_t);
@@ -84,14 +84,14 @@ public:
     void write_spi(
         unit_t unit,
         const uhd::spi_config_t &config,
-        boost::uint32_t data,
+        uint32_t data,
         size_t num_bits
     );
 
-    boost::uint32_t read_write_spi(
+    uint32_t read_write_spi(
         unit_t unit,
         const uhd::spi_config_t &config,
-        boost::uint32_t data,
+        uint32_t data,
         size_t num_bits
     );
     void set_fe_connection(
diff --git a/host/lib/usrp/x300/x300_fw_ctrl.cpp b/host/lib/usrp/x300/x300_fw_ctrl.cpp
index 25960ede0..080d235a4 100644
--- a/host/lib/usrp/x300/x300_fw_ctrl.cpp
+++ b/host/lib/usrp/x300/x300_fw_ctrl.cpp
@@ -48,7 +48,7 @@ public:
         __flush();
     }
 
-    void poke32(const wb_addr_type addr, const boost::uint32_t data)
+    void poke32(const wb_addr_type addr, const uint32_t data)
     {
         for (size_t i = 1; i <= num_retries; i++)
         {
@@ -67,14 +67,14 @@ public:
         }
     }
 
-    boost::uint32_t peek32(const wb_addr_type addr)
+    uint32_t peek32(const wb_addr_type addr)
     {
         for (size_t i = 1; i <= num_retries; i++)
         {
             boost::mutex::scoped_lock lock(reg_access);
             try
             {
-                boost::uint32_t data = this->__peek32(addr);
+                uint32_t data = this->__peek32(addr);
                 return data;
             }
             catch(const uhd::io_error &ex)
@@ -91,8 +91,8 @@ public:
 protected:
     bool errors;
 
-    virtual void __poke32(const wb_addr_type addr, const boost::uint32_t data) = 0;
-    virtual boost::uint32_t __peek32(const wb_addr_type addr) = 0;
+    virtual void __poke32(const wb_addr_type addr, const uint32_t data) = 0;
+    virtual uint32_t __peek32(const wb_addr_type addr) = 0;
     virtual void __flush() = 0;
 
     boost::mutex reg_access;
@@ -116,12 +116,12 @@ public:
     }
 
 protected:
-    virtual void __poke32(const wb_addr_type addr, const boost::uint32_t data)
+    virtual void __poke32(const wb_addr_type addr, const uint32_t data)
     {
         //load request struct
         x300_fw_comms_t request = x300_fw_comms_t();
-        request.flags = uhd::htonx<boost::uint32_t>(X300_FW_COMMS_FLAGS_ACK | X300_FW_COMMS_FLAGS_POKE32);
-        request.sequence = uhd::htonx<boost::uint32_t>(seq++);
+        request.flags = uhd::htonx<uint32_t>(X300_FW_COMMS_FLAGS_ACK | X300_FW_COMMS_FLAGS_POKE32);
+        request.sequence = uhd::htonx<uint32_t>(seq++);
         request.addr = uhd::htonx(addr);
         request.data = uhd::htonx(data);
 
@@ -135,7 +135,7 @@ protected:
         if (nbytes == 0) throw uhd::io_error("x300 fw poke32 - reply timed out");
 
         //sanity checks
-        const size_t flags = uhd::ntohx<boost::uint32_t>(reply.flags);
+        const size_t flags = uhd::ntohx<uint32_t>(reply.flags);
         UHD_ASSERT_THROW(nbytes == sizeof(reply));
         UHD_ASSERT_THROW(not (flags & X300_FW_COMMS_FLAGS_ERROR));
         UHD_ASSERT_THROW(flags & X300_FW_COMMS_FLAGS_POKE32);
@@ -145,12 +145,12 @@ protected:
         UHD_ASSERT_THROW(reply.data == request.data);
     }
 
-    virtual boost::uint32_t __peek32(const wb_addr_type addr)
+    virtual uint32_t __peek32(const wb_addr_type addr)
     {
         //load request struct
         x300_fw_comms_t request = x300_fw_comms_t();
-        request.flags = uhd::htonx<boost::uint32_t>(X300_FW_COMMS_FLAGS_ACK | X300_FW_COMMS_FLAGS_PEEK32);
-        request.sequence = uhd::htonx<boost::uint32_t>(seq++);
+        request.flags = uhd::htonx<uint32_t>(X300_FW_COMMS_FLAGS_ACK | X300_FW_COMMS_FLAGS_PEEK32);
+        request.sequence = uhd::htonx<uint32_t>(seq++);
         request.addr = uhd::htonx(addr);
         request.data = 0;
 
@@ -164,7 +164,7 @@ protected:
         if (nbytes == 0) throw uhd::io_error("x300 fw peek32 - reply timed out");
 
         //sanity checks
-        const size_t flags = uhd::ntohx<boost::uint32_t>(reply.flags);
+        const size_t flags = uhd::ntohx<uint32_t>(reply.flags);
         UHD_ASSERT_THROW(nbytes == sizeof(reply));
         UHD_ASSERT_THROW(not (flags & X300_FW_COMMS_FLAGS_ERROR));
         UHD_ASSERT_THROW(flags & X300_FW_COMMS_FLAGS_PEEK32);
@@ -173,7 +173,7 @@ protected:
         UHD_ASSERT_THROW(reply.addr == request.addr);
 
         //return result!
-        return uhd::ntohx<boost::uint32_t>(reply.data);
+        return uhd::ntohx<uint32_t>(reply.data);
     }
 
     virtual void __flush(void)
@@ -202,14 +202,14 @@ public:
 
         //Verify that the Ettus FPGA loaded in the device. This may not be true if the
         //user is switching to UHD after using LabVIEW FPGA.
-        boost::uint32_t pcie_fpga_signature = 0;
+        uint32_t pcie_fpga_signature = 0;
         _drv_proxy->peek(FPGA_PCIE_SIG_REG, pcie_fpga_signature);
         if (pcie_fpga_signature != FPGA_X3xx_SIG_VALUE)
             throw uhd::io_error("cannot create x300_ctrl_iface_pcie. incorrect/no fpga image");
 
         //Also, poll on the ZPU_STATUS bit to ensure all the state machines in the FPGA are
         //ready to accept register transaction requests.
-        boost::uint32_t reg_data = 0xffffffff;
+        uint32_t reg_data = 0xffffffff;
         boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
         boost::posix_time::time_duration elapsed;
 
@@ -232,10 +232,10 @@ public:
     }
 
 protected:
-    virtual void __poke32(const wb_addr_type addr, const boost::uint32_t data)
+    virtual void __poke32(const wb_addr_type addr, const uint32_t data)
     {
         nirio_status status = 0;
-        boost::uint32_t reg_data = 0xffffffff;
+        uint32_t reg_data = 0xffffffff;
         boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
         boost::posix_time::time_duration elapsed;
 
@@ -257,10 +257,10 @@ protected:
             throw uhd::io_error("x300 fw poke32 - operation timed out");
     }
 
-    virtual boost::uint32_t __peek32(const wb_addr_type addr)
+    virtual uint32_t __peek32(const wb_addr_type addr)
     {
         nirio_status status = 0;
-        boost::uint32_t reg_data = 0xffffffff;
+        uint32_t reg_data = 0xffffffff;
         boost::posix_time::ptime start_time = boost::posix_time::microsec_clock::local_time();
         boost::posix_time::time_duration elapsed;
 
@@ -292,8 +292,8 @@ protected:
 
 private:
     niriok_proxy::sptr _drv_proxy;
-    static const boost::uint32_t READ_TIMEOUT_IN_MS = 10;
-    static const boost::uint32_t INIT_TIMEOUT_IN_MS = 5000;
+    static const uint32_t READ_TIMEOUT_IN_MS = 10;
+    static const uint32_t INIT_TIMEOUT_IN_MS = 5000;
 };
 
 wb_iface::sptr x300_make_ctrl_iface_enet(uhd::transport::udp_simple::sptr udp, bool enable_errors = true)
diff --git a/host/lib/usrp/x300/x300_fw_uart.cpp b/host/lib/usrp/x300/x300_fw_uart.cpp
index 7f60e26fc..6e7425c4d 100644
--- a/host/lib/usrp/x300/x300_fw_uart.cpp
+++ b/host/lib/usrp/x300/x300_fw_uart.cpp
@@ -48,7 +48,7 @@ struct x300_uart_iface : uart_iface
     {
         const int shift = ((txoffset%4) * 8);
         if (shift == 0) txword32 = 0;
-        txword32 |= boost::uint32_t(ch) << shift;
+        txword32 |= uint32_t(ch) << shift;
         // Write out full 32 bit words or whatever we have if end of string
         if (txoffset % 4 == 3 or ch == '\n')
         {
@@ -82,15 +82,15 @@ struct x300_uart_iface : uart_iface
 
     void update_cache(void)
     {
-        boost::uint32_t device_rxoffset = _iface->peek32(SR_ADDR(X300_FW_SHMEM_BASE, X300_FW_SHMEM_UART_RX_INDEX));
-        boost::uint32_t delta = device_rxoffset - rxoffset;
+        uint32_t device_rxoffset = _iface->peek32(SR_ADDR(X300_FW_SHMEM_BASE, X300_FW_SHMEM_UART_RX_INDEX));
+        uint32_t delta = device_rxoffset - rxoffset;
 
         while (delta)
         {
             if (delta >= poolsize*4)
             {
                 // all the data is new - reload the entire cache
-                for (boost::uint32_t i = 0; i < poolsize; i++)
+                for (uint32_t i = 0; i < poolsize; i++)
                     _rxcache[i] = _iface->peek32(SR_ADDR(rxpool, i));
 
                 // set rxoffset to the end of the first string
@@ -104,7 +104,7 @@ struct x300_uart_iface : uart_iface
             else if (rxoffset == _last_device_rxoffset)
             {
                 // new data was added - refresh the portion of the cache that was updated
-                for (boost::uint32_t i = ((_last_device_rxoffset+1)/4) % poolsize; i != (((device_rxoffset)/4)+1) % poolsize; i = (i+1) % poolsize)
+                for (uint32_t i = ((_last_device_rxoffset+1)/4) % poolsize; i != (((device_rxoffset)/4)+1) % poolsize; i = (i+1) % poolsize)
                 {
                     _rxcache[i] = _iface->peek32(SR_ADDR(rxpool, i));
                 }
@@ -155,9 +155,9 @@ struct x300_uart_iface : uart_iface
     }
 
     wb_iface::sptr _iface;
-    boost::uint32_t rxoffset, txoffset, txword32, rxpool, txpool, poolsize;
-    boost::uint32_t _last_device_rxoffset;
-    std::vector<boost::uint32_t> _rxcache;
+    uint32_t rxoffset, txoffset, txword32, rxpool, txpool, poolsize;
+    uint32_t _last_device_rxoffset;
+    std::vector<uint32_t> _rxcache;
     std::string _rxbuff;
     boost::mutex _read_mutex;
     boost::mutex _write_mutex;
diff --git a/host/lib/usrp/x300/x300_image_loader.cpp b/host/lib/usrp/x300/x300_image_loader.cpp
index e8a1b5269..f08b21f9b 100644
--- a/host/lib/usrp/x300/x300_image_loader.cpp
+++ b/host/lib/usrp/x300/x300_image_loader.cpp
@@ -61,13 +61,13 @@ using namespace uhd::transport;
  * Packet structure
  */
 typedef struct {
-    boost::uint32_t flags;
-    boost::uint32_t sector;
-    boost::uint32_t index;
-    boost::uint32_t size;
+    uint32_t flags;
+    uint32_t sector;
+    uint32_t index;
+    uint32_t size;
     union {
-        boost::uint8_t  data8[X300_PACKET_SIZE_BYTES];
-        boost::uint16_t data16[X300_PACKET_SIZE_BYTES/2];
+        uint8_t  data8[X300_PACKET_SIZE_BYTES];
+        uint16_t data16[X300_PACKET_SIZE_BYTES/2];
     };
 } x300_fpga_update_data_t;
 
@@ -86,10 +86,10 @@ typedef struct {
     std::string                      resource;
     std::string                      filepath;
     std::string                      rpc_port;
-    boost::uint32_t                  size;
+    uint32_t                  size;
     udp_simple::sptr                 xport;
     std::vector<char>                bitstream; // .bin image extracted from .lvbitx file
-    boost::uint8_t                   data_in[udp_simple::mtu];
+    uint8_t                   data_in[udp_simple::mtu];
 } x300_session_t;
 
 /*
@@ -139,7 +139,7 @@ static void x300_validate_image(x300_session_t &session){
         if(!session.ethernet) session.bitstream.clear();
     }
     else if(extension == ".bin" or extension == ".bit"){
-        boost::uint32_t max_size = (extension == ".bin") ? X300_FPGA_BIN_SIZE_BYTES
+        uint32_t max_size = (extension == ".bin") ? X300_FPGA_BIN_SIZE_BYTES
                                                          : X300_FPGA_BIT_SIZE_BYTES;
 
         session.size = fs::file_size(session.filepath);
@@ -221,10 +221,10 @@ static void x300_setup_session(x300_session_t &session,
  * Ethernet communication functions
  */
 static UHD_INLINE size_t x300_send_and_recv(udp_simple::sptr xport,
-                                            boost::uint32_t pkt_code,
+                                            uint32_t pkt_code,
                                             x300_fpga_update_data_t *pkt_out,
-                                            boost::uint8_t* data){
-    pkt_out->flags = uhd::htonx<boost::uint32_t>(pkt_code);
+                                            uint8_t* data){
+    pkt_out->flags = uhd::htonx<uint32_t>(pkt_code);
     xport->send(boost::asio::buffer(pkt_out, sizeof(*pkt_out)));
     return xport->recv(boost::asio::buffer(data, udp_simple::mtu), UDP_TIMEOUT);
 }
@@ -236,7 +236,7 @@ static UHD_INLINE bool x300_recv_ok(const x300_fpga_update_data_t *pkt_in,
 }
 
 // Image data needs to be bitswapped
-static UHD_INLINE void x300_bitswap(boost::uint8_t *num){
+static UHD_INLINE void x300_bitswap(uint8_t *num){
     *num = ((*num & 0xF0) >> 4) | ((*num & 0x0F) << 4);
     *num = ((*num & 0xCC) >> 2) | ((*num & 0x33) << 2);
     *num = ((*num & 0xAA) >> 1) | ((*num & 0x55) << 1);
@@ -249,7 +249,7 @@ static void x300_ethernet_load(x300_session_t &session){
     const x300_fpga_update_data_t *pkt_in = reinterpret_cast<const x300_fpga_update_data_t*>(session.data_in);
 
     // Initialize write session
-    boost::uint32_t flags = X300_FPGA_PROG_FLAGS_ACK | X300_FPGA_PROG_FLAGS_INIT;
+    uint32_t flags = X300_FPGA_PROG_FLAGS_ACK | X300_FPGA_PROG_FLAGS_INIT;
     size_t len = x300_send_and_recv(session.xport, flags, &pkt_out, session.data_in);
     if(x300_recv_ok(pkt_in, len)){
         std::cout << "-- Initializing FPGA loading..." << std::flush;
@@ -290,9 +290,9 @@ static void x300_ethernet_load(x300_session_t &session){
             if(session.verify) flags |= X300_FPGA_PROG_FLAGS_VERIFY;
 
             // Set burn location
-            pkt_out.sector = htonx<boost::uint32_t>(X300_FPGA_SECTOR_START + (i/X300_FLASH_SECTOR_SIZE));
-            pkt_out.index  = htonx<boost::uint32_t>((j % X300_FLASH_SECTOR_SIZE) / 2);
-            pkt_out.size   = htonx<boost::uint32_t>(X300_PACKET_SIZE_BYTES / 2);
+            pkt_out.sector = htonx<uint32_t>(X300_FPGA_SECTOR_START + (i/X300_FLASH_SECTOR_SIZE));
+            pkt_out.index  = htonx<uint32_t>((j % X300_FLASH_SECTOR_SIZE) / 2);
+            pkt_out.size   = htonx<uint32_t>(X300_PACKET_SIZE_BYTES / 2);
 
             // Read next piece of image
             memset(pkt_out.data8, 0, X300_PACKET_SIZE_BYTES);
@@ -309,7 +309,7 @@ static void x300_ethernet_load(x300_session_t &session){
                 x300_bitswap(&pkt_out.data8[k]);
             }
             for(size_t k = 0; k < (X300_PACKET_SIZE_BYTES/2); k++){
-                pkt_out.data16[k] = htonx<boost::uint16_t>(pkt_out.data16[k]);
+                pkt_out.data16[k] = htonx<uint16_t>(pkt_out.data16[k]);
             }
 
             len = x300_send_and_recv(session.xport, flags, &pkt_out, session.data_in);
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 776fac928..959245135 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -91,8 +91,8 @@ static device_addrs_t x300_find_with_addr(const device_addr_t &hint)
 
     //load request struct
     x300_fw_comms_t request = x300_fw_comms_t();
-    request.flags = uhd::htonx<boost::uint32_t>(X300_FW_COMMS_FLAGS_ACK);
-    request.sequence = uhd::htonx<boost::uint32_t>(std::rand());
+    request.flags = uhd::htonx<uint32_t>(X300_FW_COMMS_FLAGS_ACK);
+    request.sequence = uhd::htonx<uint32_t>(std::rand());
 
     //send request
     comm->send(asio::buffer(&request, sizeof(request)));
@@ -358,17 +358,17 @@ static void x300_load_fw(wb_iface::sptr fw_reg_ctrl, const std::string &file_nam
 
     //load file into memory
     std::ifstream fw_file(file_name.c_str());
-    boost::uint32_t fw_file_buff[X300_FW_NUM_BYTES/sizeof(boost::uint32_t)];
+    uint32_t fw_file_buff[X300_FW_NUM_BYTES/sizeof(uint32_t)];
     fw_file.read((char *)fw_file_buff, sizeof(fw_file_buff));
     fw_file.close();
 
     //Poke the fw words into the WB boot loader
     fw_reg_ctrl->poke32(SR_ADDR(BOOT_LDR_BASE, BL_ADDRESS), 0);
-    for (size_t i = 0; i < X300_FW_NUM_BYTES; i+=sizeof(boost::uint32_t))
+    for (size_t i = 0; i < X300_FW_NUM_BYTES; i+=sizeof(uint32_t))
     {
         //@TODO: FIXME: Since x300_ctrl_iface acks each write and traps exceptions, the first try for the last word
         //              written will print an error because it triggers a FW reload and fails to reply.
-        fw_reg_ctrl->poke32(SR_ADDR(BOOT_LDR_BASE, BL_DATA), uhd::byteswap(fw_file_buff[i/sizeof(boost::uint32_t)]));
+        fw_reg_ctrl->poke32(SR_ADDR(BOOT_LDR_BASE, BL_DATA), uhd::byteswap(fw_file_buff[i/sizeof(uint32_t)]));
         if ((i & 0x1fff) == 0) UHD_MSG(status) << "." << std::flush;
     }
 
@@ -445,16 +445,16 @@ void x300_impl::mboard_members_t::discover_eth(
             );
 
             if (addr == boost::asio::ip::address_v4(
-                boost::uint32_t(X300_DEFAULT_IP_ETH0_1G)).to_string()) {
+                uint32_t(X300_DEFAULT_IP_ETH0_1G)).to_string()) {
                 conn_iface.type = X300_IFACE_ETH0;
             } else if (addr == boost::asio::ip::address_v4(
-                boost::uint32_t(X300_DEFAULT_IP_ETH1_1G)).to_string()) {
+                uint32_t(X300_DEFAULT_IP_ETH1_1G)).to_string()) {
                 conn_iface.type = X300_IFACE_ETH1;
             } else if (addr == boost::asio::ip::address_v4(
-                boost::uint32_t(X300_DEFAULT_IP_ETH0_10G)).to_string()) {
+                uint32_t(X300_DEFAULT_IP_ETH0_10G)).to_string()) {
                 conn_iface.type = X300_IFACE_ETH0;
             } else if (addr == boost::asio::ip::address_v4(
-                boost::uint32_t(X300_DEFAULT_IP_ETH1_10G)).to_string()) {
+                uint32_t(X300_DEFAULT_IP_ETH1_10G)).to_string()) {
                 conn_iface.type = X300_IFACE_ETH1;
             } else {
                 throw uhd::assertion_error(str(boost::format(
@@ -555,7 +555,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
         nirio_status_to_exception(status, "x300_impl: Could not initialize RIO session.");
 
         //Tell the quirks object which FIFOs carry TX stream data
-        const boost::uint32_t tx_data_fifos[2] = {X300_RADIO_DEST_PREFIX_TX, X300_RADIO_DEST_PREFIX_TX + 3};
+        const uint32_t tx_data_fifos[2] = {X300_RADIO_DEST_PREFIX_TX, X300_RADIO_DEST_PREFIX_TX + 3};
         mb.rio_fpga_interface->get_kernel_proxy()->get_rio_quirks().register_tx_streams(tx_data_fifos, 2);
 
         _tree->create<size_t>(mb_path / "mtu/recv").set(X300_PCIE_RX_DATA_FRAME_SIZE);
@@ -849,7 +849,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
     ////////////////////////////////////////////////////////////////////
     // Create the GPSDO control
     ////////////////////////////////////////////////////////////////////
-    static const boost::uint32_t dont_look_for_gpsdo = 0x1234abcdul;
+    static const uint32_t dont_look_for_gpsdo = 0x1234abcdul;
 
     //otherwise if not disabled, look for the internal GPSDO
     if (mb.zpu_ctrl->peek32(SR_ADDR(X300_FW_SHMEM_BASE, X300_FW_SHMEM_GPSDO_STATUS)) != dont_look_for_gpsdo)
@@ -1048,8 +1048,8 @@ uint32_t x300_impl::allocate_pcie_dma_chan(const uhd::sid_t &tx_sid, const xport
     }
 }
 
-static boost::uint32_t extract_sid_from_pkt(void* pkt, size_t) {
-    return uhd::sid_t(uhd::wtohx(static_cast<const boost::uint32_t*>(pkt)[1])).get_dst();
+static uint32_t extract_sid_from_pkt(void* pkt, size_t) {
+    return uhd::sid_t(uhd::wtohx(static_cast<const uint32_t*>(pkt)[1])).get_dst();
 }
 
 uhd::both_xports_t x300_impl::make_transport(
@@ -1251,8 +1251,8 @@ uhd::both_xports_t x300_impl::make_transport(
         //YES, get a __send__ buffer from the __recv__ socket
         //-- this is the only way to program the framer for recv:
         managed_send_buffer::sptr buff = xports.recv->get_send_buff();
-        buff->cast<boost::uint32_t *>()[0] = 0; //eth dispatch looks for != 0
-        buff->cast<boost::uint32_t *>()[1] = uhd::htonx(xports.send_sid.get());
+        buff->cast<uint32_t *>()[0] = 0; //eth dispatch looks for != 0
+        buff->cast<uint32_t *>()[1] = uhd::htonx(xports.send_sid.get());
         buff->commit(8);
         buff.reset();
 
@@ -1413,7 +1413,7 @@ void x300_impl::sync_times(mboard_members_t &mb, const uhd::time_spec_t& t)
     mb.fw_regmap->clock_ctrl_reg.write(fw_regmap_t::clk_ctrl_reg_t::TIME_SYNC, 0);
 }
 
-bool x300_impl::wait_for_clk_locked(mboard_members_t& mb, boost::uint32_t which, double timeout)
+bool x300_impl::wait_for_clk_locked(mboard_members_t& mb, uint32_t which, double timeout)
 {
     boost::system_time timeout_time = boost::get_system_time() + boost::posix_time::milliseconds(timeout * 1000.0);
     do {
@@ -1439,7 +1439,7 @@ bool x300_impl::is_pps_present(mboard_members_t& mb)
 {
     // The ZPU_RB_CLK_STATUS_PPS_DETECT bit toggles with each rising edge of the PPS.
     // We monitor it for up to 1.5 seconds looking for it to toggle.
-    boost::uint32_t pps_detect = mb.fw_regmap->clock_status_reg.read(fw_regmap_t::clk_status_reg_t::PPS_DETECT);
+    uint32_t pps_detect = mb.fw_regmap->clock_status_reg.read(fw_regmap_t::clk_status_reg_t::PPS_DETECT);
     for (int i = 0; i < 15; i++)
     {
         boost::this_thread::sleep(boost::posix_time::milliseconds(100));
@@ -1494,16 +1494,16 @@ x300_impl::frame_size_t x300_impl::determine_max_frame_size(const std::string &a
     udp_simple::sptr udp = udp_simple::make_connected(addr,
             BOOST_STRINGIZE(X300_MTU_DETECT_UDP_PORT));
 
-    std::vector<boost::uint8_t> buffer(std::max(user_frame_size.recv_frame_size, user_frame_size.send_frame_size));
+    std::vector<uint8_t> buffer(std::max(user_frame_size.recv_frame_size, user_frame_size.send_frame_size));
     x300_mtu_t *request = reinterpret_cast<x300_mtu_t *>(&buffer.front());
     static const double echo_timeout = 0.020; //20 ms
 
     //test holler - check if its supported in this fw version
-    request->flags = uhd::htonx<boost::uint32_t>(X300_MTU_DETECT_ECHO_REQUEST);
-    request->size = uhd::htonx<boost::uint32_t>(sizeof(x300_mtu_t));
+    request->flags = uhd::htonx<uint32_t>(X300_MTU_DETECT_ECHO_REQUEST);
+    request->size = uhd::htonx<uint32_t>(sizeof(x300_mtu_t));
     udp->send(boost::asio::buffer(buffer, sizeof(x300_mtu_t)));
     udp->recv(boost::asio::buffer(buffer), echo_timeout);
-    if (!(uhd::ntohx<boost::uint32_t>(request->flags) & X300_MTU_DETECT_ECHO_REPLY))
+    if (!(uhd::ntohx<uint32_t>(request->flags) & X300_MTU_DETECT_ECHO_REPLY))
         throw uhd::not_implemented_error("Holler protocol not implemented");
 
     //Reducing range of (min,max) by setting max value to 10gig max_frame_size as larger sizes are not supported
@@ -1517,8 +1517,8 @@ x300_impl::frame_size_t x300_impl::determine_max_frame_size(const std::string &a
     {
        size_t test_frame_size = (max_recv_frame_size/2 + min_recv_frame_size/2 + 3) & ~3;
 
-       request->flags = uhd::htonx<boost::uint32_t>(X300_MTU_DETECT_ECHO_REQUEST);
-       request->size = uhd::htonx<boost::uint32_t>(test_frame_size);
+       request->flags = uhd::htonx<uint32_t>(X300_MTU_DETECT_ECHO_REQUEST);
+       request->size = uhd::htonx<uint32_t>(test_frame_size);
        udp->send(boost::asio::buffer(buffer, sizeof(x300_mtu_t)));
 
        size_t len = udp->recv(boost::asio::buffer(buffer), echo_timeout);
@@ -1537,13 +1537,13 @@ x300_impl::frame_size_t x300_impl::determine_max_frame_size(const std::string &a
     {
         size_t test_frame_size = (max_send_frame_size/2 + min_send_frame_size/2 + 3) & ~3;
 
-        request->flags = uhd::htonx<boost::uint32_t>(X300_MTU_DETECT_ECHO_REQUEST);
-        request->size = uhd::htonx<boost::uint32_t>(sizeof(x300_mtu_t));
+        request->flags = uhd::htonx<uint32_t>(X300_MTU_DETECT_ECHO_REQUEST);
+        request->size = uhd::htonx<uint32_t>(sizeof(x300_mtu_t));
         udp->send(boost::asio::buffer(buffer, test_frame_size));
 
         size_t len = udp->recv(boost::asio::buffer(buffer), echo_timeout);
         if (len >= sizeof(x300_mtu_t))
-            len = uhd::ntohx<boost::uint32_t>(request->size);
+            len = uhd::ntohx<uint32_t>(request->size);
 
         if (len >= test_frame_size)
             min_send_frame_size = test_frame_size;
@@ -1571,9 +1571,9 @@ x300_impl::frame_size_t x300_impl::determine_max_frame_size(const std::string &a
 
 void x300_impl::check_fw_compat(const fs_path &mb_path, wb_iface::sptr iface)
 {
-    boost::uint32_t compat_num = iface->peek32(SR_ADDR(X300_FW_SHMEM_BASE, X300_FW_SHMEM_COMPAT_NUM));
-    boost::uint32_t compat_major = (compat_num >> 16);
-    boost::uint32_t compat_minor = (compat_num & 0xffff);
+    uint32_t compat_num = iface->peek32(SR_ADDR(X300_FW_SHMEM_BASE, X300_FW_SHMEM_COMPAT_NUM));
+    uint32_t compat_major = (compat_num >> 16);
+    uint32_t compat_minor = (compat_num & 0xffff);
 
     if (compat_major != X300_FW_COMPAT_MAJOR)
     {
@@ -1590,9 +1590,9 @@ void x300_impl::check_fw_compat(const fs_path &mb_path, wb_iface::sptr iface)
 
 void x300_impl::check_fpga_compat(const fs_path &mb_path, const mboard_members_t &members)
 {
-    boost::uint32_t compat_num = members.zpu_ctrl->peek32(SR_ADDR(SET0_BASE, ZPU_RB_COMPAT_NUM));
-    boost::uint32_t compat_major = (compat_num >> 16);
-    boost::uint32_t compat_minor = (compat_num & 0xffff);
+    uint32_t compat_num = members.zpu_ctrl->peek32(SR_ADDR(SET0_BASE, ZPU_RB_COMPAT_NUM));
+    uint32_t compat_major = (compat_num >> 16);
+    uint32_t compat_minor = (compat_num & 0xffff);
 
     if (compat_major != X300_FPGA_COMPAT_MAJOR)
     {
@@ -1623,7 +1623,7 @@ void x300_impl::check_fpga_compat(const fs_path &mb_path, const mboard_members_t
     _tree->create<std::string>(mb_path / "fpga_version").set(str(boost::format("%u.%u")
                 % compat_major % compat_minor));
 
-    const boost::uint32_t git_hash = members.zpu_ctrl->peek32(SR_ADDR(SET0_BASE,
+    const uint32_t git_hash = members.zpu_ctrl->peek32(SR_ADDR(SET0_BASE,
                                                               ZPU_RB_GIT_HASH));
     _tree->create<std::string>(mb_path / "fpga_version_hash").set(
         str(boost::format("%07x%s")
@@ -1637,7 +1637,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
 
     //Detect the PCIe product ID to distinguish between X300 and X310
     nirio_status status = NiRio_Status_Success;
-    boost::uint32_t pid;
+    uint32_t pid;
     niriok_proxy::sptr discovery_proxy =
         niusrprio_session::create_kernel_proxy(resource, rpc_port);
     if (discovery_proxy) {
@@ -1696,9 +1696,9 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
     x300_mboard_t mb_type = UNKNOWN;
     if (not mb_eeprom["product"].empty())
     {
-        boost::uint16_t product_num = 0;
+        uint16_t product_num = 0;
         try {
-            product_num = boost::lexical_cast<boost::uint16_t>(mb_eeprom["product"]);
+            product_num = boost::lexical_cast<uint16_t>(mb_eeprom["product"]);
         } catch (const boost::bad_lexical_cast &) {
             product_num = 0;
         }
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp
index 5d3fa4fed..ff18b1a22 100644
--- a/host/lib/usrp/x300/x300_impl.hpp
+++ b/host/lib/usrp/x300/x300_impl.hpp
@@ -266,7 +266,7 @@ private:
     void sync_times(mboard_members_t&, const uhd::time_spec_t&);
 
     uhd::sensor_value_t get_ref_locked(mboard_members_t& mb);
-    bool wait_for_clk_locked(mboard_members_t& mb, boost::uint32_t which, double timeout);
+    bool wait_for_clk_locked(mboard_members_t& mb, uint32_t which, double timeout);
     bool is_pps_present(mboard_members_t& mb);
 
     void set_mb_eeprom(uhd::i2c_iface::sptr i2c, const uhd::usrp::mboard_eeprom_t &);
diff --git a/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp b/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp
index 991b97696..4bb9c9fb5 100644
--- a/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp
+++ b/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp
@@ -82,11 +82,11 @@ UHD_RFNOC_RADIO_BLOCK_CONSTRUCTOR(x300_radio_ctrl)
     if (_radio_type==PRIMARY) {
         _fp_gpio = gpio_atr::gpio_atr_3000::make(ctrl, regs::sr_addr(regs::FP_GPIO), regs::RB_FP_GPIO);
         BOOST_FOREACH(const gpio_atr::gpio_attr_map_t::value_type attr, gpio_atr::gpio_attr_map) {
-            _tree->create<boost::uint32_t>(fs_path("gpio") / "FP0" / attr.second)
+            _tree->create<uint32_t>(fs_path("gpio") / "FP0" / attr.second)
                 .set(0)
                 .add_coerced_subscriber(boost::bind(&gpio_atr::gpio_atr_3000::set_gpio_attr, _fp_gpio, attr.first, _1));
         }
-        _tree->create<boost::uint32_t>(fs_path("gpio") / "FP0" / "READBACK")
+        _tree->create<uint32_t>(fs_path("gpio") / "FP0" / "READBACK")
             .set_publisher(boost::bind(&gpio_atr::gpio_atr_3000::read_gpio, _fp_gpio));
     }
 
@@ -125,9 +125,10 @@ UHD_RFNOC_RADIO_BLOCK_CONSTRUCTOR(x300_radio_ctrl)
         // Bind the daughterboard command time to the motherboard level property
         ////////////////////////////////////////////////////////////////
 
-        if (_tree->exists(fs_path("time") / "cmd")) {
+        if (_tree->exists(fs_path("time") / "cmd") and
+                _tree->exists(fs_path("dboards" / _radio_slot /  "rx_frontends" / _rx_fe_map.at(i).db_fe_name / "time" / "cmd"))) {
             _tree->access<time_spec_t>(fs_path("time") / "cmd")
-                    .add_coerced_subscriber(boost::bind(&x300_radio_ctrl_impl::set_fe_cmd_time, this, _1, i));
+                .add_coerced_subscriber(boost::bind(&x300_radio_ctrl_impl::set_fe_cmd_time, this, _1, i));
         }
     }
 
@@ -172,11 +173,11 @@ double x300_radio_ctrl_impl::set_rate(double /* rate */)
     return get_rate();
 }
 
-time_spec_t x300_radio_ctrl_impl::set_fe_cmd_time(const time_spec_t &time, const size_t chan)
+void x300_radio_ctrl_impl::set_fe_cmd_time(const time_spec_t &time, const size_t chan)
 {
-    return _tree->access<time_spec_t>(
+    _tree->access<time_spec_t>(
             fs_path("dboards" / _radio_slot /  "rx_frontends" / _rx_fe_map.at(chan).db_fe_name / "time" / "cmd")
-    ).set(time).get();
+    ).set(time);
 }
 
 void x300_radio_ctrl_impl::set_tx_antenna(const std::string &ant, const size_t chan)
@@ -483,7 +484,7 @@ void x300_radio_ctrl_impl::reset_codec()
     _dac->reset();
 }
 
-void x300_radio_ctrl_impl::self_test_adc(boost::uint32_t ramp_time_ms)
+void x300_radio_ctrl_impl::self_test_adc(uint32_t ramp_time_ms)
 {
     //Bypass all front-end corrections
     for (size_t i = 0; i < _get_num_radios(); i++) {
@@ -602,7 +603,7 @@ void x300_radio_ctrl_impl::synchronize_dacs(const std::vector<x300_radio_ctrl_im
         boost::posix_time::microsec_clock::local_time() - t_start;
 
     //Add 100% of headroom + uncertaintly to the command time
-    boost::uint64_t t_sync_us = (t_elapsed.total_microseconds() * 2) + 13000 /*Scheduler latency*/;
+    uint64_t t_sync_us = (t_elapsed.total_microseconds() * 2) + 13000 /*Scheduler latency*/;
 
     //Pick radios[0] as the time reference.
     uhd::time_spec_t sync_time =
@@ -653,7 +654,7 @@ double x300_radio_ctrl_impl::self_cal_adc_xfer_delay(
         double delay = clock->set_clock_delay(X300_CLOCK_WHICH_ADC0, delay_incr*i + delay_start);
         wait_for_clk_locked(0.1);
 
-        boost::uint32_t err_code = 0;
+        uint32_t err_code = 0;
         for (size_t r = 0; r < radios.size(); r++) {
             //Test each channel (I and Q) individually so as to not accidentally trigger
             //on the data from the other channel if there is a swap
@@ -784,20 +785,20 @@ void x300_radio_ctrl_impl::_self_cal_adc_capture_delay(bool print_status)
 {
     if (print_status) UHD_MSG(status) << "Running ADC capture delay self-cal..." << std::flush;
 
-    static const boost::uint32_t NUM_DELAY_STEPS = 32;   //The IDELAYE2 element has 32 steps
-    static const boost::uint32_t NUM_RETRIES     = 2;    //Retry self-cal if it fails in warmup situations
-    static const boost::int32_t  MIN_WINDOW_LEN  = 4;
+    static const uint32_t NUM_DELAY_STEPS = 32;   //The IDELAYE2 element has 32 steps
+    static const uint32_t NUM_RETRIES     = 2;    //Retry self-cal if it fails in warmup situations
+    static const int32_t  MIN_WINDOW_LEN  = 4;
 
-    boost::int32_t win_start = -1, win_stop = -1;
-    boost::uint32_t iter = 0;
+    int32_t win_start = -1, win_stop = -1;
+    uint32_t iter = 0;
     while (iter++ < NUM_RETRIES) {
-        for (boost::uint32_t dly_tap = 0; dly_tap < NUM_DELAY_STEPS; dly_tap++) {
+        for (uint32_t dly_tap = 0; dly_tap < NUM_DELAY_STEPS; dly_tap++) {
             //Apply delay
             _regs->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_VAL, dly_tap);
             _regs->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 1);
             _regs->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 0);
 
-            boost::uint32_t err_code = 0;
+            uint32_t err_code = 0;
 
             // -- Test I Channel --
             //Put ADC in ramp test mode. Tie the other channel to all ones.
@@ -868,7 +869,7 @@ void x300_radio_ctrl_impl::_self_cal_adc_capture_delay(bool print_status)
         throw uhd::runtime_error("self_cal_adc_capture_delay: Self calibration failed. Valid window too narrow.");
     }
 
-    boost::uint32_t ideal_tap = (win_stop + win_start) / 2;
+    uint32_t ideal_tap = (win_stop + win_start) / 2;
     _regs->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_VAL, ideal_tap);
     _regs->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 1);
     _regs->misc_outs_reg.write(radio_regmap_t::misc_outs_reg_t::ADC_DATA_DLY_STB, 0);
@@ -879,14 +880,14 @@ void x300_radio_ctrl_impl::_self_cal_adc_capture_delay(bool print_status)
     }
 }
 
-void x300_radio_ctrl_impl::_check_adc(const boost::uint32_t val)
+void x300_radio_ctrl_impl::_check_adc(const uint32_t val)
 {
     //Wait for previous control transaction to flush
     user_reg_read64(regs::RB_TEST);
     //Wait for ADC test pattern to propagate
     boost::this_thread::sleep(boost::posix_time::microsec(5));
     //Read value of RX readback register and verify
-    boost::uint32_t adc_rb = static_cast<boost::uint32_t>(user_reg_read64(regs::RB_TEST)>>32);
+    uint32_t adc_rb = static_cast<uint32_t>(user_reg_read64(regs::RB_TEST)>>32);
     adc_rb ^= 0xfffc0000; //adapt for I inversion in FPGA
     if (val != adc_rb) {
         throw uhd::runtime_error(
diff --git a/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp b/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp
index 5b9d47841..6e17778bd 100644
--- a/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp
+++ b/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp
@@ -82,7 +82,7 @@ public:
     void reset_codec();
 
     void self_test_adc(
-        boost::uint32_t ramp_time_ms = 100);
+        uint32_t ramp_time_ms = 100);
 
     static void extended_adc_test(
         const std::vector<x300_radio_ctrl_impl::sptr>&, double duration_s);
@@ -154,14 +154,14 @@ private:
 
     void _self_cal_adc_capture_delay(bool print_status);
 
-    void _check_adc(const boost::uint32_t val);
+    void _check_adc(const uint32_t val);
 
     void _set_db_eeprom(uhd::i2c_iface::sptr i2c, const size_t, const uhd::usrp::dboard_eeprom_t &);
 
     void set_rx_fe_corrections(const uhd::fs_path &db_path, const uhd::fs_path &rx_fe_corr_path, const double lo_freq);
     void set_tx_fe_corrections(const uhd::fs_path &db_path, const uhd::fs_path &tx_fe_corr_path, const double lo_freq);
 
-    time_spec_t set_fe_cmd_time(const time_spec_t &time, const size_t chan);
+    void set_fe_cmd_time(const time_spec_t &time, const size_t chan);
 
 private: // members
     enum radio_connection_t { PRIMARY, SECONDARY };
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index 80d275949..6e7c47a64 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -184,9 +184,9 @@ namespace uhd { namespace usrp { namespace x300 {
             UHD_DEFINE_SOFT_REG_FIELD(GPSDO_PWR_EN, /*width*/ 1, /*shift*/ 6);  //[6]
             UHD_DEFINE_SOFT_REG_FIELD(TIME_SYNC,    /*width*/ 1, /*shift*/ 7);  //[7]
 
-            static const boost::uint32_t SRC_EXTERNAL = 0x0;
-            static const boost::uint32_t SRC_INTERNAL = 0x2;
-            static const boost::uint32_t SRC_GPSDO    = 0x3;
+            static const uint32_t SRC_EXTERNAL = 0x0;
+            static const uint32_t SRC_INTERNAL = 0x2;
+            static const uint32_t SRC_GPSDO    = 0x3;
 
             clk_ctrl_reg_t(): uhd::soft_reg32_wo_t(SR_ADDR(SET0_BASE, ZPU_SR_CLOCK_CTRL)) {
                 //Initial values