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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2014-03-15 20:43:51 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2014-03-15 20:43:51 -0700 |
| commit | 4726c0c0958c776bccdf9898384e335013c7e811 (patch) | |
| tree | 08c179bc422238013574108b56b5a29d73280cd9 /host/lib/usrp/x300/x300_impl.hpp | |
| parent | 4022711d4ffc1b05780e5e4c4bd2bb176fb41c95 (diff) | |
| parent | 9126069560de0a462f58596055dad15b35693dce (diff) | |
| download | uhd-4726c0c0958c776bccdf9898384e335013c7e811.tar.gz uhd-4726c0c0958c776bccdf9898384e335013c7e811.tar.bz2 uhd-4726c0c0958c776bccdf9898384e335013c7e811.zip | |
Merge clock and PPS fixes.
Diffstat (limited to 'host/lib/usrp/x300/x300_impl.hpp')
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index 1e159ef38..8f4ae8264 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -205,11 +205,11 @@ private: gpio_core_200::sptr fp_gpio; //clock control register bits - int clock_control_regs__clock_source; - int clock_control_regs__pps_select; - int clock_control_regs__pps_out_enb; - int clock_control_regs__tcxo_enb; - int clock_control_regs__gpsdo_pwr; + int clock_control_regs_clock_source; + int clock_control_regs_pps_select; + int clock_control_regs_pps_out_enb; + int clock_control_regs_tcxo_enb; + int clock_control_regs_gpsdo_pwr; //which FPGA image is loaded std::string loaded_fpga_image; @@ -323,6 +323,8 @@ private: void update_time_source(mboard_members_t&, const std::string &); uhd::sensor_value_t get_ref_locked(uhd::wb_iface::sptr); + void wait_for_ref_locked(uhd::wb_iface::sptr, double timeout = 0.0); + bool is_pps_present(uhd::wb_iface::sptr); void set_db_eeprom(uhd::i2c_iface::sptr i2c, const size_t, const uhd::usrp::dboard_eeprom_t &); void set_mb_eeprom(uhd::i2c_iface::sptr i2c, const uhd::usrp::mboard_eeprom_t &); |