usrp-e100: reset dboard clocks on rate change, and dont cache in dboard iface

3 files changed, 32 insertions, 4 deletions

diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
index b0bf20b67..1ac2b804c 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp
@@ -287,6 +287,9 @@ public:
         if (_out_rate == rate) return;
         if (rate == 61.44e6) set_clock_settings_with_external_vcxo(rate);
         else                 set_clock_settings_with_internal_vco(rate);
+        //clock rate changed! update dboard clocks and FPGA ticks per second
+        set_rx_dboard_clock_rate(rate);
+        set_tx_dboard_clock_rate(rate);
         _iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate()));
     }
 
@@ -328,6 +331,7 @@ public:
 
     void set_rx_dboard_clock_rate(double rate){
         assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate");
+        _rx_clock_rate = rate;
         size_t divider = size_t(this->_chan_rate/rate);
         //set the divider registers
         set_clock_divider(divider,
@@ -340,6 +344,10 @@ public:
         this->latch_regs();
     }
 
+    double get_rx_clock_rate(void){
+        return _rx_clock_rate;
+    }
+
     /***********************************************************************
      * TX Dboard Clock Control (output 6, divider 2)
      **********************************************************************/
@@ -358,6 +366,7 @@ public:
 
     void set_tx_dboard_clock_rate(double rate){
         assert_has(get_tx_dboard_clock_rates(), rate, "tx dboard clock rate");
+        _tx_clock_rate = rate;
         size_t divider = size_t(this->_chan_rate/rate);
         //set the divider registers
         set_clock_divider(divider,
@@ -369,7 +378,11 @@ public:
         this->send_reg(0x197);
         this->latch_regs();
     }
-    
+
+    double get_tx_clock_rate(void){
+        return _tx_clock_rate;
+    }
+
     /***********************************************************************
      * Clock reference control
      **********************************************************************/
@@ -401,6 +414,7 @@ private:
     ad9522_regs_t _ad9522_regs;
     double _out_rate; //rate at the fpga and codec
     double _chan_rate; //rate before final dividers
+    double _rx_clock_rate, _tx_clock_rate;
 
     void latch_regs(void){
         _ad9522_regs.io_update = 1;
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
index 623fbc73b..507f914f3 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp
+++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp
@@ -79,6 +79,18 @@ public:
     virtual void set_tx_dboard_clock_rate(double rate) = 0;
 
     /*!
+     * Get the current rx dboard clock rate.
+     * \return the clock rate in Hz
+     */
+    virtual double get_rx_clock_rate(void) = 0;
+
+    /*!
+     * Get the current tx dboard clock rate.
+     * \return the clock rate in Hz
+     */
+    virtual double get_tx_clock_rate(void) = 0;
+
+    /*!
      * Enable/disable the rx dboard clock.
      * \param enb true to enable
      */
diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/usrp_e100/dboard_iface.cpp
index 4ee354486..61b5a1c92 100644
--- a/host/lib/usrp/usrp_e100/dboard_iface.cpp
+++ b/host/lib/usrp/usrp_e100/dboard_iface.cpp
@@ -97,7 +97,6 @@ private:
     usrp_e100_iface::sptr _iface;
     usrp_e100_clock_ctrl::sptr _clock;
     usrp_e100_codec_ctrl::sptr _codec;
-    uhd::dict<unit_t, double> _clock_rates;
 };
 
 /***********************************************************************
@@ -115,7 +114,6 @@ dboard_iface::sptr make_usrp_e100_dboard_iface(
  * Clock Rates
  **********************************************************************/
 void usrp_e100_dboard_iface::set_clock_rate(unit_t unit, double rate){
-    _clock_rates[unit] = rate;
     switch(unit){
     case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate);
     case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate);
@@ -131,7 +129,11 @@ std::vector<double> usrp_e100_dboard_iface::get_clock_rates(unit_t unit){
 }
 
 double usrp_e100_dboard_iface::get_clock_rate(unit_t unit){
-    return _clock_rates[unit];
+    switch(unit){
+    case UNIT_RX: return _clock->get_rx_clock_rate();
+    case UNIT_TX: return _clock->get_tx_clock_rate();
+    }
+    UHD_THROW_INVALID_CODE_PATH();
 }
 
 void usrp_e100_dboard_iface::set_clock_enabled(unit_t unit, bool enb){