usrp2: prefix the dsp and ctrl registers with 0 in preparation for 2nd dsp

4 files changed, 52 insertions, 48 deletions

diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp
index 8340f7cdd..5cf48fe96 100644
--- a/host/lib/usrp/usrp2/dsp_impl.cpp
+++ b/host/lib/usrp/usrp2/dsp_impl.cpp
@@ -98,7 +98,7 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){
 
     case DSP_PROP_FREQ_SHIFT:{
             double new_freq = val.as<double>();
-            _iface->poke32(_iface->regs.dsp_rx_freq,
+            _iface->poke32(_iface->regs.dsp0_rx_freq,
                 dsp_type1::calc_cordic_word_and_update(new_freq, get_master_clock_freq())
             );
             _ddc_freq = new_freq; //shadow
@@ -110,11 +110,11 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){
             _ddc_decim = pick_closest_rate(extact_rate, _allowed_decim_and_interp_rates);
 
             //set the decimation
-            _iface->poke32(_iface->regs.dsp_rx_decim_rate, dsp_type1::calc_cic_filter_word(_ddc_decim));
+            _iface->poke32(_iface->regs.dsp0_rx_decim_rate, dsp_type1::calc_cic_filter_word(_ddc_decim));
 
             //set the scaling
             static const boost::int16_t default_rx_scale_iq = 1024;
-            _iface->poke32(_iface->regs.dsp_rx_scale_iq,
+            _iface->poke32(_iface->regs.dsp0_rx_scale_iq,
                 dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
             );
         }
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 397fae636..d8ce9824d 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -87,17 +87,17 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     }
 
     //setup the vrt rx registers
-    _iface->poke32(_iface->regs.rx_ctrl_clear_overrun, 1); //reset
-    _iface->poke32(_iface->regs.rx_ctrl_nsamps_per_pkt, recv_samps_per_packet);
-    _iface->poke32(_iface->regs.rx_ctrl_nchannels, 1);
-    _iface->poke32(_iface->regs.rx_ctrl_vrt_header, 0
+    _iface->poke32(_iface->regs.rx_ctrl0_clear_overrun, 1); //reset
+    _iface->poke32(_iface->regs.rx_ctrl0_nsamps_per_pkt, recv_samps_per_packet);
+    _iface->poke32(_iface->regs.rx_ctrl0_nchannels, 1);
+    _iface->poke32(_iface->regs.rx_ctrl0_vrt_header, 0
         | (0x1 << 28) //if data with stream id
         | (0x1 << 26) //has trailer
         | (0x3 << 22) //integer time other
         | (0x1 << 20) //fractional time sample count
     );
-    _iface->poke32(_iface->regs.rx_ctrl_vrt_stream_id, usrp2_impl::RECV_SID);
-    _iface->poke32(_iface->regs.rx_ctrl_vrt_trailer, 0);
+    _iface->poke32(_iface->regs.rx_ctrl0_vrt_stream_id, usrp2_impl::RECV_SID);
+    _iface->poke32(_iface->regs.rx_ctrl0_vrt_trailer, 0);
     _iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq()));
 
     //init the tx control registers
@@ -164,7 +164,7 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     this->issue_ddc_stream_cmd(stream_cmd);
     data_transport->get_recv_buff().get(); //recv with timeout for lingering
     data_transport->get_recv_buff().get(); //recv with timeout for expected
-    _iface->poke32(_iface->regs.rx_ctrl_clear_overrun, 1); //resets sequence
+    _iface->poke32(_iface->regs.rx_ctrl0_clear_overrun, 1); //resets sequence
 }
 
 usrp2_mboard_impl::~usrp2_mboard_impl(void){
@@ -273,9 +273,9 @@ void usrp2_mboard_impl::handle_overflow(void){
 
 void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
     _continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS;
-    _iface->poke32(_iface->regs.rx_ctrl_stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
-    _iface->poke32(_iface->regs.rx_ctrl_time_secs,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
-    _iface->poke32(_iface->regs.rx_ctrl_time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
+    _iface->poke32(_iface->regs.rx_ctrl0_stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
+    _iface->poke32(_iface->regs.rx_ctrl0_time_secs,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+    _iface->poke32(_iface->regs.rx_ctrl0_time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
 }
 
 /***********************************************************************
@@ -401,7 +401,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){
         //sanity check
         UHD_ASSERT_THROW(_rx_subdev_spec.size() == 1);
         //set the mux
-        _iface->poke32(_iface->regs.dsp_rx_mux, dsp_type1::calc_rx_mux_word(
+        _iface->poke32(_iface->regs.dsp0_rx_mux, dsp_type1::calc_rx_mux_word(
             _dboard_manager->get_rx_subdev(_rx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
         ));
         return;
diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index 84907c32e..2159c4276 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -38,8 +38,10 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.sr_udp_sm = 96;
   x.sr_tx_dsp = 208;
   x.sr_tx_ctrl = 224;
-  x.sr_rx_dsp = 160;
-  x.sr_rx_ctrl = 176;
+  x.sr_rx_dsp0 = 160;
+  x.sr_rx_ctrl0 = 176;
+  x.sr_rx_dsp1 = 240;
+  x.sr_rx_ctrl1 = 32;
   x.sr_time64 = 192;
   x.sr_simtimer = 198;
   x.sr_last = 255;
@@ -68,12 +70,12 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1);
   x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2);
   x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4);
-  x.dsp_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp + 0);
-  x.dsp_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp + 1);
-  x.dsp_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp + 2);
-  x.dsp_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp + 3);
-  x.dsp_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp + 4);
-  x.dsp_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp + 5);
+  x.dsp0_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0);
+  x.dsp0_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1);
+  x.dsp0_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2);
+  x.dsp0_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3);
+  x.dsp0_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4);
+  x.dsp0_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5);
   x.gpio_io = gpio_base + 0;
   x.gpio_ddr = gpio_base + 4;
   x.gpio_tx_sel = gpio_base + 8;
@@ -86,15 +88,15 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.atr_inrx_rxside = atr_base + 10;
   x.atr_full_txside = atr_base + 12;
   x.atr_full_rxside = atr_base + 14;
-  x.rx_ctrl_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl + 0);
-  x.rx_ctrl_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl + 1);
-  x.rx_ctrl_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl + 2);
-  x.rx_ctrl_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl + 3);
-  x.rx_ctrl_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl + 4);
-  x.rx_ctrl_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl + 5);
-  x.rx_ctrl_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl + 6);
-  x.rx_ctrl_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl + 7);
-  x.rx_ctrl_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl + 8);
+  x.rx_ctrl0_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0);
+  x.rx_ctrl0_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1);
+  x.rx_ctrl0_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2);
+  x.rx_ctrl0_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3);
+  x.rx_ctrl0_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4);
+  x.rx_ctrl0_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5);
+  x.rx_ctrl0_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6);
+  x.rx_ctrl0_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7);
+  x.rx_ctrl0_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8);
   x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0);
   x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1);
   x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2);
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 977b342cb..e150528a7 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -38,8 +38,10 @@ typedef struct {
     int sr_udp_sm;
     int sr_tx_dsp;
     int sr_tx_ctrl;
-    int sr_rx_dsp;
-    int sr_rx_ctrl;
+    int sr_rx_dsp0;
+    int sr_rx_ctrl0;
+    int sr_rx_dsp1;
+    int sr_rx_ctrl1;
     int sr_time64;
     int sr_simtimer;
     int sr_last;
@@ -68,12 +70,12 @@ typedef struct {
     int dsp_tx_scale_iq;
     int dsp_tx_interp_rate;
     int dsp_tx_mux;
-    int dsp_rx_freq;
-    int dsp_rx_scale_iq;
-    int dsp_rx_decim_rate;
-    int dsp_rx_dcoffset_i;
-    int dsp_rx_dcoffset_q;
-    int dsp_rx_mux;
+    int dsp0_rx_freq;
+    int dsp0_rx_scale_iq;
+    int dsp0_rx_decim_rate;
+    int dsp0_rx_dcoffset_i;
+    int dsp0_rx_dcoffset_q;
+    int dsp0_rx_mux;
     int gpio_base;
     int gpio_io;
     int gpio_ddr;
@@ -88,15 +90,15 @@ typedef struct {
     int atr_inrx_rxside;
     int atr_full_txside;
     int atr_full_rxside;
-    int rx_ctrl_stream_cmd;
-    int rx_ctrl_time_secs;
-    int rx_ctrl_time_ticks;
-    int rx_ctrl_clear_overrun;
-    int rx_ctrl_vrt_header;
-    int rx_ctrl_vrt_stream_id;
-    int rx_ctrl_vrt_trailer;
-    int rx_ctrl_nsamps_per_pkt;
-    int rx_ctrl_nchannels;
+    int rx_ctrl0_stream_cmd;
+    int rx_ctrl0_time_secs;
+    int rx_ctrl0_time_ticks;
+    int rx_ctrl0_clear_overrun;
+    int rx_ctrl0_vrt_header;
+    int rx_ctrl0_vrt_stream_id;
+    int rx_ctrl0_vrt_trailer;
+    int rx_ctrl0_nsamps_per_pkt;
+    int rx_ctrl0_nchannels;
     int tx_ctrl_num_chan;
     int tx_ctrl_clear_state;
     int tx_ctrl_report_sid;