usrp2: implemented clear state for RX and TX control, and zero sample command support

4 files changed, 6 insertions, 35 deletions

diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index 39e6c167f..844df603c 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -241,8 +241,6 @@ void usrp2_impl::io_impl::recv_pirate_loop(
 /***********************************************************************
  * Helper Functions
  **********************************************************************/
-#include <uhd/usrp/mboard_props.hpp> //TODO remove when hack below is fixed
-
 void usrp2_impl::io_init(void){
 
     //the assumption is that all data transports should be identical
@@ -252,29 +250,6 @@ void usrp2_impl::io_init(void){
     //create new io impl
     _io_impl = UHD_PIMPL_MAKE(io_impl, (num_recv_frames, send_frame_size, _data_transports.size()));
 
-    //TODO temporary fix for weird power up state, remove when FPGA fixed
-    {
-        //send an initial packet to all transports
-        tx_metadata_t md; md.end_of_burst = true;
-        this->send(
-            std::vector<const void *>(_data_transports.size(), NULL), 0, md,
-            io_type_t::COMPLEX_FLOAT32, device::SEND_MODE_ONE_PACKET, 0
-        );
-
-        //issue a stream command to each motherboard
-        BOOST_FOREACH(usrp2_mboard_impl::sptr mboard, _mboards){
-            (*mboard)[MBOARD_PROP_STREAM_CMD] = stream_cmd_t(stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS);
-        }
-
-        //wait
-        boost::this_thread::sleep(boost::posix_time::milliseconds(100));
-
-        //flush all transport receive queues (no timeout)
-        BOOST_FOREACH(zero_copy_if::sptr xport, _data_transports){
-            while(xport->get_recv_buff(0).get() != NULL){};
-        }
-    }
-
     //create a new pirate thread for each zc if (yarr!!)
     for (size_t i = 0; i < _data_transports.size(); i++){
         _io_impl->recv_pirate_crew.create_thread(boost::bind(
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index bb9b6d1a9..d4dc8a4bd 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -40,7 +40,6 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     const device_addr_t &flow_control_hints
 ):
     _index(index),
-    _recv_samps_per_packet(recv_samps_per_packet),
     _iface(usrp2_iface::make(ctrl_transport))
 {
     //Send a small data packet so the usrp2 knows the udp source port.
@@ -74,9 +73,9 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     }
 
     //init the rx control registers
-    _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _recv_samps_per_packet);
+    _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset
+    _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, recv_samps_per_packet);
     _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1);
-    _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset
     _iface->poke32(U2_REG_RX_CTRL_VRT_HEADER, 0
         | (0x1 << 28) //if data with stream id
         | (0x1 << 26) //has trailer
@@ -88,8 +87,8 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq()));
 
     //init the tx control registers
-    _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
     _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset
+    _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
     _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1);  //sid 1 (different from rx)
     _iface->poke32(U2_REG_TX_CTRL_POLICY, U2_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
 
@@ -97,6 +96,7 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     const double ups_per_sec = flow_control_hints.cast<double>("ups_per_sec", 100);
     const size_t cycles_per_up = size_t(_clock_ctrl->get_master_clock_rate()/ups_per_sec);
     _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, U2_FLAG_TX_CTRL_UP_ENB | cycles_per_up);
+    _iface->poke32(U2_REG_TX_CTRL_CYCLES_PER_UP, 0); //cycles per update is disabled
 
     //setting the packets per update
     const double ups_per_fifo = flow_control_hints.cast<double>("ups_per_fifo", 8);
@@ -187,7 +187,6 @@ void usrp2_mboard_impl::set_time_spec(const time_spec_t &time_spec, bool now){
 }
 
 void usrp2_mboard_impl::handle_overflow(void){
-    _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1);
     if (_continuous_streaming){ //re-issue the stream command if already continuous
         this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
     }
@@ -195,9 +194,7 @@ void usrp2_mboard_impl::handle_overflow(void){
 
 void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
     _continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS;
-    _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, dsp_type1::calc_stream_cmd_word(
-        stream_cmd, _recv_samps_per_packet
-    ));
+    _iface->poke32(U2_REG_RX_CTRL_STREAM_CMD, dsp_type1::calc_stream_cmd_word(stream_cmd));
     _iface->poke32(U2_REG_RX_CTRL_TIME_SECS,  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
     _iface->poke32(U2_REG_RX_CTRL_TIME_TICKS, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
 }
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index e4980a539..e41cefc10 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -98,7 +98,6 @@ public:
 
 private:
     size_t _index;
-    const size_t _recv_samps_per_packet;
     bool _continuous_streaming;
 
     //interfaces
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index c3a4d22de..cef7cf2e6 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -179,7 +179,7 @@
 #define U2_REG_RX_CTRL_TIME_SECS         _SR_ADDR(SR_RX_CTRL + 1)
 #define U2_REG_RX_CTRL_TIME_TICKS        _SR_ADDR(SR_RX_CTRL + 2)
 
-#define U2_REG_RX_CTRL_CLEAR_OVERRUN     _SR_ADDR(SR_RX_CTRL + 3) // write anything to clear overrun
+#define U2_REG_RX_CTRL_CLEAR_STATE       _SR_ADDR(SR_RX_CTRL + 3)
 #define U2_REG_RX_CTRL_VRT_HEADER        _SR_ADDR(SR_RX_CTRL + 4) // word 0 of packet.  FPGA fills in packet counter
 #define U2_REG_RX_CTRL_VRT_STREAM_ID     _SR_ADDR(SR_RX_CTRL + 5) // word 1 of packet.
 #define U2_REG_RX_CTRL_VRT_TRAILER       _SR_ADDR(SR_RX_CTRL + 6)