Merge branch 'tx_report'

Conflicts:
	host/lib/usrp/usrp2/io_impl.cpp

4 files changed, 53 insertions, 5 deletions

diff --git a/host/lib/usrp/usrp2/io_impl.cpp b/host/lib/usrp/usrp2/io_impl.cpp
index 7e7ce40a2..aa6d15783 100644
--- a/host/lib/usrp/usrp2/io_impl.cpp
+++ b/host/lib/usrp/usrp2/io_impl.cpp
@@ -32,6 +32,8 @@ using namespace uhd::usrp;
 using namespace uhd::transport;
 namespace asio = boost::asio;
 
+static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET;
+
 /***********************************************************************
  * io impl details (internal to this file)
  * - pirate crew
@@ -44,7 +46,8 @@ struct usrp2_impl::io_impl{
 
     io_impl(size_t num_frames, size_t width):
         packet_handler_recv_state(width),
-        recv_pirate_booty(alignment_buffer_type::make(num_frames, width))
+        recv_pirate_booty(alignment_buffer_type::make(num_frames, width)),
+        async_msg_fifo(bounded_buffer<async_metadata_t>::make(100/*messages deep*/))
     {
         /* NOP */
     }
@@ -69,6 +72,7 @@ struct usrp2_impl::io_impl{
     boost::thread_group recv_pirate_crew;
     bool recv_pirate_crew_raiding;
     alignment_buffer_type::sptr recv_pirate_booty;
+    bounded_buffer<async_metadata_t>::sptr async_msg_fifo;
 };
 
 /***********************************************************************
@@ -93,12 +97,31 @@ void usrp2_impl::io_impl::recv_pirate_loop(
             //extract the vrt header packet info
             vrt::if_packet_info_t if_packet_info;
             if_packet_info.num_packet_words32 = buff->size()/sizeof(boost::uint32_t);
-            vrt::if_hdr_unpack_be(buff->cast<const boost::uint32_t *>(), if_packet_info);
+            const boost::uint32_t *vrt_hdr = buff->cast<const boost::uint32_t *>();
+            vrt::if_hdr_unpack_be(vrt_hdr, if_packet_info);
+
+            //handle a tx async report message
+            if (if_packet_info.sid == 1 and if_packet_info.packet_type != vrt::if_packet_info_t::PACKET_TYPE_DATA){
+
+                //fill in the async metadata
+                async_metadata_t metadata;
+                metadata.channel = index;
+                metadata.has_time_spec = if_packet_info.has_tsi and if_packet_info.has_tsf;
+                metadata.time_spec = time_spec_t(
+                    time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), mboard->get_master_clock_freq()
+                );
+                metadata.event_code = vrt_packet_handler::get_context_code<async_metadata_t::event_code_t>(vrt_hdr, if_packet_info);
+
+                //print the famous U, and push the metadata into the message queue
+                if (metadata.event_code & underflow_flags) std::cerr << "U";
+                async_msg_fifo->push_with_pop_on_full(metadata);
+                continue;
+            }
 
             //handle the packet count / sequence number
             if (if_packet_info.packet_count != next_packet_seq){
                 //std::cerr << "S" << (if_packet_info.packet_count - next_packet_seq)%16;
-                std::cerr << "O"; //report overrun (drops in the kernel)
+                std::cerr << "O"; //report overflow (drops in the kernel)
             }
             next_packet_seq = (if_packet_info.packet_count+1)%16;
 
@@ -150,6 +173,18 @@ void usrp2_impl::io_init(void){
 }
 
 /***********************************************************************
+ * Async Data
+ **********************************************************************/
+bool usrp2_impl::recv_async_msg(
+    async_metadata_t &async_metadata, size_t timeout_ms
+){
+    boost::this_thread::disable_interruption di; //disable because the wait can throw
+    return _io_impl->async_msg_fifo->pop_with_timed_wait(
+        async_metadata, boost::posix_time::milliseconds(timeout_ms)
+    );
+}
+
+/***********************************************************************
  * Send Data
  **********************************************************************/
 bool get_send_buffs(
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 7518d3114..b3b03c11c 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -67,7 +67,7 @@ usrp2_mboard_impl::usrp2_mboard_impl(
         _allowed_decim_and_interp_rates.push_back(i);
     }
 
-    //setup the vrt rx registers
+    //init the rx control registers
     _iface->poke32(U2_REG_RX_CTRL_NSAMPS_PER_PKT, _io_helper.get_max_recv_samps_per_packet());
     _iface->poke32(U2_REG_RX_CTRL_NCHANNELS, 1);
     _iface->poke32(U2_REG_RX_CTRL_CLEAR_OVERRUN, 1); //reset
@@ -81,6 +81,11 @@ usrp2_mboard_impl::usrp2_mboard_impl(
     _iface->poke32(U2_REG_RX_CTRL_VRT_TRAILER, 0);
     _iface->poke32(U2_REG_TIME64_TPS, size_t(get_master_clock_freq()));
 
+    //init the tx control registers
+    _iface->poke32(U2_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
+    _iface->poke32(U2_REG_TX_CTRL_CLEAR_STATE, 1); //reset
+    _iface->poke32(U2_REG_TX_CTRL_REPORT_SID, 1);  //sid 1 (different from rx)
+
     //init the ddc
     init_ddc_config();
 
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index cae1b21d6..2eaf12350 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -235,6 +235,7 @@ public:
         uhd::rx_metadata_t &, const uhd::io_type_t &,
         uhd::device::recv_mode_t, size_t
     );
+    bool recv_async_msg(uhd::async_metadata_t &, size_t);
 
 private:
     //device properties interface
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index 1a5864c85..aa8bd860f 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -226,7 +226,7 @@
 #define U2_REG_ATR_FULL_RXSIDE  U2_REG_ATR_BASE + 14
 
 ///////////////////////////////////////////////////
-// VITA RX CTRL regs
+// RX CTRL regs
 ///////////////////////////////////////////////////
 // The following 3 are logically a single command register.
 // They are clocked into the underlying fifo when time_ticks is written.
@@ -241,4 +241,11 @@
 #define U2_REG_RX_CTRL_NSAMPS_PER_PKT    _SR_ADDR(SR_RX_CTRL + 7)
 #define U2_REG_RX_CTRL_NCHANNELS         _SR_ADDR(SR_RX_CTRL + 8) // 1 in basic case, up to 4 for vector sources
 
+///////////////////////////////////////////////////
+// TX CTRL regs
+///////////////////////////////////////////////////
+#define U2_REG_TX_CTRL_NUM_CHAN          _SR_ADDR(SR_TX_CTRL + 0)
+#define U2_REG_TX_CTRL_CLEAR_STATE       _SR_ADDR(SR_TX_CTRL + 1)
+#define U2_REG_TX_CTRL_REPORT_SID        _SR_ADDR(SR_TX_CTRL + 2)
+
 #endif /* INCLUDED_USRP2_REGS_HPP */