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author | Josh Blum <josh@joshknows.com> | 2010-07-07 02:23:38 +0000 |
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committer | Josh Blum <josh@joshknows.com> | 2010-07-07 02:23:38 +0000 |
commit | f2e9d3ed0941dc5738149dd82d1eac158bdf0a0f (patch) | |
tree | 82a350987e32cd329ab5fe56b6dd9fbfef08230f /host/lib/usrp/usrp2/usrp2_regs.hpp | |
parent | 998fee6ef064f1d53a61dd0eec79276d1e85291e (diff) | |
parent | 5c2cccfe8c4a9c6c912a4d18dc1e7a6f84c79609 (diff) | |
download | uhd-f2e9d3ed0941dc5738149dd82d1eac158bdf0a0f.tar.gz uhd-f2e9d3ed0941dc5738149dd82d1eac158bdf0a0f.tar.bz2 uhd-f2e9d3ed0941dc5738149dd82d1eac158bdf0a0f.zip |
Merge branch 'master' of ettus.sourcerepo.com:ettus/uhdpriv into usrp_e
Conflicts:
host/examples/rx_timed_samples.cpp
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp')
-rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 589fa71a3..c859d3603 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -18,8 +18,6 @@ #ifndef INCLUDED_USRP2_REGS_HPP #define INCLUDED_USRP2_REGS_HPP -#include <boost/cstdint.hpp> - //////////////////////////////////////////////////// // Settings Bus, Slave #7, Not Byte Addressable! // @@ -46,7 +44,7 @@ #define SR_SIMTIMER 198 #define SR_LAST 255 -#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(boost::uint32_t)) +#define _SR_ADDR(sr) ((MISC_OUTPUT_BASE) + (4*(sr))) ///////////////////////////////////////////////// // SPI Slave Constants @@ -104,7 +102,11 @@ #define U2_REG_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS #define U2_REG_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS #define U2_REG_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above -#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define U2_REG_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) +#define U2_REG_TIME64_TPS _SR_ADDR(SR_TIME64 + 4) // the ticks per second rollover count + +#define U2_REG_TIME64_SECS_RB (0xCC00 + 4*10) +#define U2_REG_TIME64_TICKS_RB (0xCC00 + 4*11) //pps flags (see above) #define U2_FLAG_TIME64_PPS_NEGEDGE (0 << 0) |