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authorJosh Blum <josh@joshknows.com>2010-04-01 15:16:29 +0000
committerJosh Blum <josh@joshknows.com>2010-04-01 15:16:29 +0000
commit8fd3ce07369a7962dc8eb5ace2007a80ad7dd907 (patch)
treebb4f5c61f8a7809af1c58d5513dc6c3e78c7a5b2 /host/lib/usrp/usrp2/usrp2_impl.cpp
parent58d71729716a688af36ba4a413e6f6ee4729eefc (diff)
parentf1f4865119605c66ffece113a621308d82512d23 (diff)
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Merge branch 'master' of git@ettus.sourcerepo.com:ettus/uhd into usrp_e
Conflicts: host/include/uhd/usrp/CMakeLists.txt
Diffstat (limited to 'host/lib/usrp/usrp2/usrp2_impl.cpp')
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.cpp25
1 files changed, 25 insertions, 0 deletions
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index b0ee395fb..b3a22e175 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -16,6 +16,7 @@
//
#include <uhd/transport/if_addrs.hpp>
+#include <uhd/usrp/device_props.hpp>
#include <uhd/utils/assert.hpp>
#include <uhd/utils/static.hpp>
#include <boost/format.hpp>
@@ -173,6 +174,30 @@ double usrp2_impl::get_master_clock_freq(void){
return 100e6;
}
+void usrp2_impl::poke(boost::uint32_t addr, boost::uint32_t data){
+ //setup the out data
+ usrp2_ctrl_data_t out_data;
+ out_data.id = htonl(USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO);
+ out_data.data.poke_args.addr = htonl(addr);
+ out_data.data.poke_args.data = htonl(data);
+
+ //send and recv
+ usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data);
+ ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE);
+}
+
+boost::uint32_t usrp2_impl::peek(boost::uint32_t addr){
+ //setup the out data
+ usrp2_ctrl_data_t out_data;
+ out_data.id = htonl(USRP2_CTRL_ID_PEEK_AT_THIS_REGISTER_FOR_ME_BRO);
+ out_data.data.poke_args.addr = htonl(addr);
+
+ //send and recv
+ usrp2_ctrl_data_t in_data = this->ctrl_send_and_recv(out_data);
+ ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_WOAH_I_DEFINITELY_PEEKED_IT_DUDE);
+ return ntohl(out_data.data.poke_args.data);
+}
+
/***********************************************************************
* Control Send/Recv
**********************************************************************/