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| author | Josh Blum <josh@joshknows.com> | 2011-02-17 13:58:27 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-02-17 13:58:27 -0800 |
| commit | c73165bb1d6ec6c714426584e3b1ef15e2e87cb4 (patch) | |
| tree | 09c7cc4b5684b2d8dca789c10346c39de9c3f2f4 /host/lib/usrp/usrp2/fw_common.h | |
| parent | c88166d65651bb98fc182ae600a6649120c601b5 (diff) | |
| download | uhd-c73165bb1d6ec6c714426584e3b1ef15e2e87cb4.tar.gz uhd-c73165bb1d6ec6c714426584e3b1ef15e2e87cb4.tar.bz2 uhd-c73165bb1d6ec6c714426584e3b1ef15e2e87cb4.zip | |
usrp2: added 2nd dsp support to firmware for 2 and N series
Diffstat (limited to 'host/lib/usrp/usrp2/fw_common.h')
| -rw-r--r-- | host/lib/usrp/usrp2/fw_common.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index a22f805e1..33c0b728a 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -31,7 +31,7 @@ extern "C" { //fpga and firmware compatibility numbers #define USRP2_FPGA_COMPAT_NUM 4 -#define USRP2_FW_COMPAT_NUM 8 +#define USRP2_FW_COMPAT_NUM 9 //used to differentiate control packets over data port #define USRP2_INVALID_VRT_HEADER 0 @@ -40,8 +40,9 @@ extern "C" { // Dynamic and/or private ports: 49152-65535 #define USRP2_UDP_CTRL_PORT 49152 //#define USRP2_UDP_UPDATE_PORT 49154 -#define USRP2_UDP_DATA_PORT 49156 +#define USRP2_UDP_DSP0_PORT 49156 #define USRP2_UDP_ERR0_PORT 49157 +#define USRP2_UDP_DSP1_PORT 49158 //////////////////////////////////////////////////////////////////////// // I2C addresses |