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| author | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:15 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:15 -0800 |
| commit | c6e63c9d2af2c0b2e168aa6fdd63fe7b214927de (patch) | |
| tree | 7d2bf4c7480f68c55eb215fcad16ef400d29dfcc /host/lib/usrp/e100 | |
| parent | 1e3cb86432ee1d695a12fd99590206e43caab2cc (diff) | |
| download | uhd-c6e63c9d2af2c0b2e168aa6fdd63fe7b214927de.tar.gz uhd-c6e63c9d2af2c0b2e168aa6fdd63fe7b214927de.tar.bz2 uhd-c6e63c9d2af2c0b2e168aa6fdd63fe7b214927de.zip | |
b100/e100: unify rx/tx fifo clears into one
Diffstat (limited to 'host/lib/usrp/e100')
| -rw-r--r-- | host/lib/usrp/e100/e100_regs.hpp | 6 | ||||
| -rw-r--r-- | host/lib/usrp/e100/io_impl.cpp | 5 |
2 files changed, 4 insertions, 7 deletions
diff --git a/host/lib/usrp/e100/e100_regs.hpp b/host/lib/usrp/e100/e100_regs.hpp index eee27b5b3..0ec5f4de3 100644 --- a/host/lib/usrp/e100/e100_regs.hpp +++ b/host/lib/usrp/e100/e100_regs.hpp @@ -116,8 +116,7 @@ #define UE_SR_TX_FRONT 54 // 5 regs (+0 to +4) #define UE_SR_REG_TEST32 60 // 1 reg -#define UE_SR_CLEAR_RX_FIFO 61 // 1 reg -#define UE_SR_CLEAR_TX_FIFO 62 // 1 reg +#define UE_SR_CLEAR_FIFO 61 // 1 reg #define UE_SR_GLOBAL_RESET 63 // 1 reg #define UE_SR_USER_REGS 64 // 2 regs @@ -131,8 +130,7 @@ ///////////////////////////////////////////////// // Magic reset regs //////////////////////////////////////////////// -#define E100_REG_CLEAR_RX E100_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO) -#define E100_REG_CLEAR_TX E100_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO) +#define E100_REG_CLEAR_FIFO E100_REG_SR_ADDR(UE_SR_CLEAR_FIFO) #define E100_REG_GLOBAL_RESET E100_REG_SR_ADDR(UE_SR_GLOBAL_RESET) #endif diff --git a/host/lib/usrp/e100/io_impl.cpp b/host/lib/usrp/e100/io_impl.cpp index 4d530585b..8c7f5e742 100644 --- a/host/lib/usrp/e100/io_impl.cpp +++ b/host/lib/usrp/e100/io_impl.cpp @@ -164,9 +164,8 @@ void e100_impl::io_init(void){ _io_impl->demuxer = recv_packet_demuxer::make(_data_transport, _rx_dsps.size(), E100_RX_SID_BASE); _io_impl->iface = _fpga_ctrl; - //clear state machines - _fpga_ctrl->poke32(E100_REG_CLEAR_RX, 0); - _fpga_ctrl->poke32(E100_REG_CLEAR_TX, 0); + //clear fifo state machines + _fpga_ctrl->poke32(E100_REG_CLEAR_FIFO, 0); //allocate streamer weak ptrs containers _rx_streamers.resize(_rx_dsps.size()); |