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authorJosh Blum <josh@joshknows.com>2012-07-02 14:08:12 -0700
committerJosh Blum <josh@joshknows.com>2012-07-16 20:44:49 -0700
commit58484632eb793b1ee1ffd06b9807023551133a1b (patch)
treea4b1d223e9d7f3036ff57c268e8a1e45fac82ad8 /host/lib/usrp/e100/dboard_iface.cpp
parent9d30b8fc24dc7efa8973a4d305b240c245133fe6 (diff)
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e100: squashed host code for fifo control/timed commands
This uses the new b100/e100 common core and FIFO control modules. Subsequent commit will be the compatible FPGA merge. Conflicts: host/lib/usrp/e100/io_impl.cpp
Diffstat (limited to 'host/lib/usrp/e100/dboard_iface.cpp')
-rw-r--r--host/lib/usrp/e100/dboard_iface.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/e100/dboard_iface.cpp b/host/lib/usrp/e100/dboard_iface.cpp
index 6afc7bc48..532b2dc9e 100644
--- a/host/lib/usrp/e100/dboard_iface.cpp
+++ b/host/lib/usrp/e100/dboard_iface.cpp
@@ -45,7 +45,7 @@ public:
_spi_iface = spi_iface;
_clock = clock;
_codec = codec;
- _gpio = gpio_core_200::make(_wb_iface, E100_REG_SR_ADDR(UE_SR_GPIO), E100_REG_RB_GPIO);
+ _gpio = gpio_core_200::make(_wb_iface, TOREG(SR_GPIO), REG_RB_GPIO);
//init the clock rate shadows
this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());