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author | Balint Seeber <balint@ettus.com> | 2013-11-19 18:38:15 -0800 |
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committer | Balint Seeber <balint@ettus.com> | 2013-11-19 18:38:15 -0800 |
commit | f568b1984f77a525260b6a5157ce3a8f1ab56307 (patch) | |
tree | 674846eeac5ca4dd742d71c9978df29f21d0e18b /host/lib/usrp/e100/clock_ctrl.cpp | |
parent | aaef714ac5db24090da8e6d5f338ebc23827e07f (diff) | |
download | uhd-f568b1984f77a525260b6a5157ce3a8f1ab56307.tar.gz uhd-f568b1984f77a525260b6a5157ce3a8f1ab56307.tar.bz2 uhd-f568b1984f77a525260b6a5157ce3a8f1ab56307.zip |
b200: extra check on loopback request to determine VREQ transfer size
Diffstat (limited to 'host/lib/usrp/e100/clock_ctrl.cpp')
0 files changed, 0 insertions, 0 deletions