UBX: Phase synchronization

- Disabled MAX2871 VCO auto selection for phase sync
- Added checks for new phase sync constraints recently published by Maxim
- Added dboard_clock_rate option for X300
- Adjusted timing of SYNC signal relative to dboard referenc clock

1 files changed, 149 insertions, 71 deletions

diff --git a/host/lib/usrp/dboard/db_ubx.cpp b/host/lib/usrp/dboard/db_ubx.cpp
index 7cb4b2d6b..0bf57cb70 100644
--- a/host/lib/usrp/dboard/db_ubx.cpp
+++ b/host/lib/usrp/dboard/db_ubx.cpp
@@ -22,6 +22,7 @@
 #include <uhd/types/dict.hpp>
 #include <uhd/types/ranges.hpp>
 #include <uhd/types/sensors.hpp>
+#include <uhd/types/direction.hpp>
 #include <uhd/usrp/dboard_base.hpp>
 #include <uhd/usrp/dboard_manager.hpp>
 #include <uhd/utils/assert_has.hpp>
@@ -92,43 +93,43 @@ struct ubx_gpio_field_info_t
 {
     ubx_gpio_field_id_t id;
     dboard_iface::unit_t unit;
-    boost::uint32_t offset;
-    boost::uint32_t mask;
-    boost::uint32_t width;
+    uint32_t offset;
+    uint32_t mask;
+    uint32_t width;
     enum {OUTPUT,INPUT} direction;
     bool is_atr_controlled;
-    boost::uint32_t atr_idle;
-    boost::uint32_t atr_tx;
-    boost::uint32_t atr_rx;
-    boost::uint32_t atr_full_duplex;
+    uint32_t atr_idle;
+    uint32_t atr_tx;
+    uint32_t atr_rx;
+    uint32_t atr_full_duplex;
 };
 
 struct ubx_gpio_reg_t
 {
     bool dirty;
-    boost::uint32_t value;
-    boost::uint32_t mask;
-    boost::uint32_t ddr;
-    boost::uint32_t atr_mask;
-    boost::uint32_t atr_idle;
-    boost::uint32_t atr_tx;
-    boost::uint32_t atr_rx;
-    boost::uint32_t atr_full_duplex;
+    uint32_t value;
+    uint32_t mask;
+    uint32_t ddr;
+    uint32_t atr_mask;
+    uint32_t atr_idle;
+    uint32_t atr_tx;
+    uint32_t atr_rx;
+    uint32_t atr_full_duplex;
 };
 
 struct ubx_cpld_reg_t
 {
-    void set_field(ubx_cpld_field_id_t field, boost::uint32_t val)
+    void set_field(ubx_cpld_field_id_t field, uint32_t val)
     {
         UHD_ASSERT_THROW(val == (val & 0x1));
 
         if (val)
-            value |= boost::uint32_t(1) << field;
+            value |= uint32_t(1) << field;
         else
-            value &= ~(boost::uint32_t(1) << field);
+            value &= ~(uint32_t(1) << field);
     }
 
-    boost::uint32_t value;
+    uint32_t value;
 };
 
 enum spi_dest_t {
@@ -181,13 +182,13 @@ static const ubx_gpio_field_info_t ubx_v1_gpio_info[] = {
     {RX_ANT,        dboard_iface::UNIT_TX,   4,  0x1<<4,     1,  ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0},
     {TX_EN_N,       dboard_iface::UNIT_TX,   5,  0x1<<5,     1,  ubx_gpio_field_info_t::INPUT,  true,   1,  0,  1,  0},
     {RX_EN_N,       dboard_iface::UNIT_TX,   6,  0x1<<6,     1,  ubx_gpio_field_info_t::INPUT,  true,   1,  1,  0,  0},
-    {TXLO1_SYNC,    dboard_iface::UNIT_TX,   7,  0x1<<7,     1,  ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0},
-    {TXLO2_SYNC,    dboard_iface::UNIT_TX,   9,  0x1<<9,     1,  ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0},
+    {TXLO1_SYNC,    dboard_iface::UNIT_TX,   7,  0x1<<7,     1,  ubx_gpio_field_info_t::INPUT,  true,   0,  0,  0,  0},
+    {TXLO2_SYNC,    dboard_iface::UNIT_TX,   9,  0x1<<9,     1,  ubx_gpio_field_info_t::INPUT,  true,   0,  0,  0,  0},
     {TX_GAIN,       dboard_iface::UNIT_TX,   10, 0x3F<<10,   10, ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0},
     {RX_LO_LOCKED,  dboard_iface::UNIT_RX,   0,  0x1,        1,  ubx_gpio_field_info_t::OUTPUT, false,  0,  0,  0,  0},
     {TX_LO_LOCKED,  dboard_iface::UNIT_RX,   1,  0x1<<1,     1,  ubx_gpio_field_info_t::OUTPUT, false,  0,  0,  0,  0},
-    {RXLO1_SYNC,    dboard_iface::UNIT_RX,   5,  0x1<<5,     1,  ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0},
-    {RXLO2_SYNC,    dboard_iface::UNIT_RX,   7,  0x1<<7,     1,  ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0},
+    {RXLO1_SYNC,    dboard_iface::UNIT_RX,   5,  0x1<<5,     1,  ubx_gpio_field_info_t::INPUT,  true,   0,  0,  0,  0},
+    {RXLO2_SYNC,    dboard_iface::UNIT_RX,   7,  0x1<<7,     1,  ubx_gpio_field_info_t::INPUT,  true,   0,  0,  0,  0},
     {RX_GAIN,       dboard_iface::UNIT_RX,   10, 0x3F<<10,   10, ubx_gpio_field_info_t::INPUT,  false,  0,  0,  0,  0}
 };
 
@@ -348,7 +349,6 @@ public:
             BOOST_FOREACH(max287x_iface::sptr lo, los)
             {
                 lo->set_auto_retune(false);
-                lo->set_clock_divider_mode(max287x_iface::CLOCK_DIV_MODE_CLOCK_DIVIDER_OFF);
                 lo->set_muxout_mode(max287x_iface::MUXOUT_DLD);
                 lo->set_ld_pin_mode(max287x_iface::LD_PIN_MODE_DLD);
             }
@@ -363,13 +363,10 @@ public:
             BOOST_FOREACH(max287x_iface::sptr lo, los)
             {
                 lo->set_auto_retune(false);
-                lo->set_clock_divider_mode(max287x_iface::CLOCK_DIV_MODE_CLOCK_DIVIDER_OFF);
                 //lo->set_cycle_slip_mode(true);  // tried it - caused longer lock times
                 lo->set_charge_pump_current(max287x_iface::CHARGE_PUMP_CURRENT_5_12MA);
                 lo->set_muxout_mode(max287x_iface::MUXOUT_SYNC);
                 lo->set_ld_pin_mode(max287x_iface::LD_PIN_MODE_DLD);
-                lo->set_low_noise_and_spur(max287x_iface::LOW_NOISE_AND_SPUR_LOW_NOISE);
-                lo->set_phase(0);
             }
         }
         else
@@ -395,6 +392,16 @@ public:
         get_rx_subtree()->create<std::string>("xcvr_mode/value")
             .subscribe(boost::bind(&ubx_xcvr::set_xcvr_mode, this, _1))
             .set("FDX");
+        get_tx_subtree()->create<std::vector<std::string> >("power_mode/options")
+            .set(ubx_power_modes);
+        get_tx_subtree()->create<std::string>("power_mode/value")
+            .subscribe(boost::bind(&uhd::property<std::string>::set, &get_rx_subtree()->access<std::string>("power_mode/value"), _1))
+            .publish(boost::bind(&uhd::property<std::string>::get, &get_rx_subtree()->access<std::string>("power_mode/value")));
+        get_tx_subtree()->create<std::vector<std::string> >("xcvr_mode/options")
+            .set(ubx_xcvr_modes);
+        get_tx_subtree()->create<std::string>("xcvr_mode/value")
+            .subscribe(boost::bind(&uhd::property<std::string>::set, &get_rx_subtree()->access<std::string>("xcvr_mode/value"), _1))
+            .publish(boost::bind(&uhd::property<std::string>::get, &get_rx_subtree()->access<std::string>("xcvr_mode/value")));
 
         ////////////////////////////////////////////////////////////////////
         // Register TX properties
@@ -428,6 +435,9 @@ public:
             .set(bw);
         get_tx_subtree()->create<meta_range_t>("bandwidth/range")
             .set(freq_range_t(bw, bw));
+        get_tx_subtree()->create<int64_t>("sync_delay")
+            .subscribe(boost::bind(&ubx_xcvr::set_sync_delay, this, true, _1))
+            .set(-8);
 
         ////////////////////////////////////////////////////////////////////
         // Register RX properties
@@ -461,6 +471,9 @@ public:
             .set(bw);
         get_rx_subtree()->create<meta_range_t>("bandwidth/range")
             .set(freq_range_t(bw, bw));
+        get_rx_subtree()->create<int64_t>("sync_delay")
+            .subscribe(boost::bind(&ubx_xcvr::set_sync_delay, this, false, _1))
+            .set(-8);
     }
 
     ~ubx_xcvr(void)
@@ -496,22 +509,22 @@ private:
     /***********************************************************************
     * Helper Functions
     **********************************************************************/
-    void write_spi_reg(spi_dest_t dest, boost::uint32_t value)
+    void write_spi_reg(spi_dest_t dest, uint32_t value)
     {
         boost::mutex::scoped_lock lock(_spi_mutex);
         ROUTE_SPI(_iface, dest);
         WRITE_SPI(_iface, value);
     }
 
-    void write_spi_regs(spi_dest_t dest, std::vector<boost::uint32_t> values)
+    void write_spi_regs(spi_dest_t dest, std::vector<uint32_t> values)
     {
         boost::mutex::scoped_lock lock(_spi_mutex);
         ROUTE_SPI(_iface, dest);
-        BOOST_FOREACH(boost::uint32_t value, values)
+        BOOST_FOREACH(uint32_t value, values)
             WRITE_SPI(_iface, value);
     }
 
-    void set_cpld_field(ubx_cpld_field_id_t id, boost::uint32_t value)
+    void set_cpld_field(ubx_cpld_field_id_t id, uint32_t value)
     {
         _cpld_reg.set_field(id, value);
     }
@@ -525,7 +538,7 @@ private:
         }
     }
 
-    void set_gpio_field(ubx_gpio_field_id_t id, boost::uint32_t value)
+    void set_gpio_field(ubx_gpio_field_id_t id, uint32_t value)
     {
         // Look up field info
         std::map<ubx_gpio_field_id_t,ubx_gpio_field_info_t>::iterator entry = _gpio_map.find(id);
@@ -535,8 +548,8 @@ private:
         if (field_info.direction == ubx_gpio_field_info_t::OUTPUT)
             return;
         ubx_gpio_reg_t *reg = (field_info.unit == dboard_iface::UNIT_TX ? &_tx_gpio_reg : &_rx_gpio_reg);
-        boost::uint32_t _value = reg->value;
-        boost::uint32_t _mask = reg->mask;
+        uint32_t _value = reg->value;
+        uint32_t _mask = reg->mask;
 
         // Set field and mask
         _value &= ~field_info.mask;
@@ -552,7 +565,7 @@ private:
         }
     }
 
-    boost::uint32_t get_gpio_field(ubx_gpio_field_id_t id)
+    uint32_t get_gpio_field(ubx_gpio_field_id_t id)
     {
         // Look up field info
         std::map<ubx_gpio_field_id_t,ubx_gpio_field_info_t>::iterator entry = _gpio_map.find(id);
@@ -566,7 +579,7 @@ private:
         }
 
         // Read register
-        boost::uint32_t value = _iface->read_gpio(field_info.unit);
+        uint32_t value = _iface->read_gpio(field_info.unit);
         value &= field_info.mask;
         value >>= field_info.offset;
 
@@ -590,6 +603,61 @@ private:
         }
     }
 
+    void sync_phase(uhd::time_spec_t cmd_time, uhd::direction_t dir)
+    {
+        // Send phase sync signal only if the command time is set
+        if (cmd_time != uhd::time_spec_t(0.0))
+        {
+            // Delay 400 microseconds to allow LOs to lock
+            cmd_time += uhd::time_spec_t(0.0004);
+
+            // Phase synchronization for MAX2871 requires that the sync signal
+            // is at least 4/(N*PFD_freq) + 2.6ns before the rising edge of the
+            // ref clock and 4/(N*PFD_freq) after the rising edge of the ref clock.
+            // Since the ref clock, the radio clock, and the VITA time are all
+            // synchronized to the 10 MHz clock, use the time spec to move
+            // the rising edge of the sync signal away from the 10 MHz edge,
+            // which will move it away from the ref clock edge by the same amount.
+            // Since the MAX2871 requires the ref freq and PFD freq be the same
+            // for phase synchronization, the dboard clock rate is used as the PFD
+            // freq and the worst case value of 20 is used for the N value to
+            // calculate the offset.
+            double pfd_freq = _iface->get_clock_rate(dir == TX_DIRECTION ? dboard_iface::UNIT_TX : dboard_iface::UNIT_RX);
+            double tick_rate = _iface->get_codec_rate(dir == TX_DIRECTION ? dboard_iface::UNIT_TX : dboard_iface::UNIT_RX);
+            int64_t ticks = cmd_time.to_ticks(tick_rate);
+            ticks -= ticks % (int64_t)(tick_rate / 10e6);            // align to 10 MHz clock
+            ticks += dir == TX_DIRECTION ? _tx_sync_delay : _rx_sync_delay;
+            ticks += std::ceil(tick_rate*4/(20*pfd_freq));  // add required offset (using worst case N value of 20)
+            cmd_time = uhd::time_spec_t::from_ticks(ticks, tick_rate);
+            _iface->set_command_time(cmd_time);
+
+            // Assert SYNC
+            ubx_gpio_field_info_t lo1_field_info = _gpio_map.find(dir == TX_DIRECTION ? TXLO1_SYNC : RXLO1_SYNC)->second;
+            ubx_gpio_field_info_t lo2_field_info = _gpio_map.find(dir == TX_DIRECTION ? TXLO2_SYNC : RXLO2_SYNC)->second;
+            uint16_t value = (1 << lo1_field_info.offset) | (1 << lo2_field_info.offset);
+            uint16_t mask = lo1_field_info.mask | lo2_field_info.mask;
+            dboard_iface::unit_t unit = lo1_field_info.unit;
+            UHD_ASSERT_THROW(lo1_field_info.unit == lo2_field_info.unit);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_IDLE, value, mask);
+            cmd_time += uhd::time_spec_t(1/pfd_freq);
+            _iface->set_command_time(cmd_time);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_TX_ONLY, value, mask);
+            cmd_time += uhd::time_spec_t(1/pfd_freq);
+            _iface->set_command_time(cmd_time);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_RX_ONLY, value, mask);
+            cmd_time += uhd::time_spec_t(1/pfd_freq);
+            _iface->set_command_time(cmd_time);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_FULL_DUPLEX, value, mask);
+
+            // De-assert SYNC
+            // Head of line blocking means the command time does not need to be set.
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_IDLE, 0, mask);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_TX_ONLY, 0, mask);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_RX_ONLY, 0, mask);
+            _iface->set_atr_reg(unit, dboard_iface::ATR_REG_FULL_DUPLEX, 0, mask);
+        }
+    }
+
     /***********************************************************************
      * Board Control Handling
      **********************************************************************/
@@ -695,6 +763,21 @@ private:
         else if (freq >= 500*fMHz and _power_mode == POWERSAVE)
             _txlo2->shutdown();
 
+        // Set up LOs for phase sync if command time is set
+        uhd::time_spec_t cmd_time = _iface->get_command_time();
+        if (cmd_time != uhd::time_spec_t(0.0))
+        {
+            _txlo1->config_for_sync(true);
+            if (not _txlo2->is_shutdown())
+                _txlo2->config_for_sync(true);
+        }
+        else
+        {
+            _txlo1->config_for_sync(false);
+            if (not _txlo2->is_shutdown())
+                _txlo2->config_for_sync(false);
+        }
+
         // Set up registers for the requested frequency
         if (freq < (500*fMHz))
         {
@@ -783,24 +866,9 @@ private:
             break;
         }
 
-        if (_txlo1->can_sync())
+        if (cmd_time != uhd::time_spec_t(0.0) and _txlo1->can_sync())
         {
-            // Send phase sync signal only if the command time is set
-            uhd::time_spec_t cmd_time = _iface->get_command_time();
-            if (cmd_time != uhd::time_spec_t(0.0))
-            {
-                // Delay 400 microseconds to allow LOs to lock
-                cmd_time += uhd::time_spec_t(0.0004);
-                _iface->set_command_time(cmd_time);
-                set_gpio_field(TXLO1_SYNC, 1);
-                set_gpio_field(TXLO2_SYNC, 1);
-                write_gpio();
-                // De-assert SYNC
-                // Head of line blocking means the time does not need to be set.
-                set_gpio_field(TXLO1_SYNC, 0);
-                set_gpio_field(TXLO2_SYNC, 0);
-                write_gpio();
-            }
+            sync_phase(cmd_time, TX_DIRECTION);
         }
 
         _tx_freq = freq_lo1 - freq_lo2;
@@ -837,6 +905,21 @@ private:
         else if (freq >= 500*fMHz and _power_mode == POWERSAVE)
             _rxlo2->shutdown();
 
+        // Set up LOs for phase sync if command time is set
+        uhd::time_spec_t cmd_time = _iface->get_command_time();
+        if (cmd_time != uhd::time_spec_t(0.0))
+        {
+            _rxlo1->config_for_sync(true);
+            if (not _rxlo2->is_shutdown())
+                _rxlo2->config_for_sync(true);
+        }
+        else
+        {
+            _rxlo1->config_for_sync(false);
+            if (not _rxlo2->is_shutdown())
+                _rxlo2->config_for_sync(false);
+        }
+
         // Work with frequencies
         if (freq < 100*fMHz)
         {
@@ -965,24 +1048,9 @@ private:
             break;
         }
 
-        if (_rxlo1->can_sync())
+        if (cmd_time != uhd::time_spec_t(0.0) and _rxlo1->can_sync())
         {
-            // Send phase sync signal only if the command time is set
-            uhd::time_spec_t cmd_time = _iface->get_command_time();
-            if (cmd_time != uhd::time_spec_t(0.0))
-            {
-                // Delay 400 microseconds to allow LOs to lock
-                cmd_time += uhd::time_spec_t(0.0004);
-                _iface->set_command_time(cmd_time);
-                set_gpio_field(RXLO1_SYNC, 1);
-                set_gpio_field(RXLO2_SYNC, 1);
-                write_gpio();
-                // De-assert SYNC
-                // Head of line blocking means the time does not need to be set.
-                set_gpio_field(RXLO1_SYNC, 0);
-                set_gpio_field(RXLO2_SYNC, 0);
-                write_gpio();
-            }
+            sync_phase(cmd_time, RX_DIRECTION);
         }
 
         _rx_freq = freq_lo1 - freq_lo2;
@@ -1051,6 +1119,14 @@ private:
         _xcvr_mode = mode;
     }
 
+    void set_sync_delay(bool is_tx, int64_t value)
+    {
+        if (is_tx)
+            _tx_sync_delay = value;
+        else
+            _rx_sync_delay = value;
+    }
+
     /***********************************************************************
     * Variables
     **********************************************************************/
@@ -1058,7 +1134,7 @@ private:
     boost::mutex _spi_mutex;
     boost::mutex _mutex;
     ubx_cpld_reg_t _cpld_reg;
-    boost::uint32_t _prev_cpld_value;
+    uint32_t _prev_cpld_value;
     boost::shared_ptr<max287x_iface> _txlo1;
     boost::shared_ptr<max287x_iface> _txlo2;
     boost::shared_ptr<max287x_iface> _rxlo1;
@@ -1086,6 +1162,8 @@ private:
     std::map<ubx_gpio_field_id_t,ubx_gpio_field_info_t> _gpio_map;
     ubx_gpio_reg_t _tx_gpio_reg;
     ubx_gpio_reg_t _rx_gpio_reg;
+    int64_t _tx_sync_delay;
+    int64_t _rx_sync_delay;
 };
 
 /***********************************************************************