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authorJosh Blum <josh@joshknows.com>2012-07-02 13:59:05 -0700
committerJosh Blum <josh@joshknows.com>2012-07-02 14:06:06 -0700
commit7a1824e8fddadd915e2d7490a8b57764b815b09f (patch)
tree7a8184baac73093c48b499100691231522363102 /host/lib/usrp/b100/dboard_iface.cpp
parentde4d2fca9030cda04de1457abe8cba6a70ba0b95 (diff)
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b100: squashed host code for fifo control/timed commands
This uses the new b100/e100 common core and FIFO control modules. Subsequent commit will be the compatible FPGA merge.
Diffstat (limited to 'host/lib/usrp/b100/dboard_iface.cpp')
-rw-r--r--host/lib/usrp/b100/dboard_iface.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/usrp/b100/dboard_iface.cpp b/host/lib/usrp/b100/dboard_iface.cpp
index 39ad5c5ac..25604da72 100644
--- a/host/lib/usrp/b100/dboard_iface.cpp
+++ b/host/lib/usrp/b100/dboard_iface.cpp
@@ -45,7 +45,7 @@ public:
_spi_iface = spi_iface;
_clock = clock;
_codec = codec;
- _gpio = gpio_core_200::make(_wb_iface, B100_REG_SR_ADDR(B100_SR_GPIO), B100_REG_RB_GPIO);
+ _gpio = gpio_core_200::make(_wb_iface, TOREG(SR_GPIO), REG_RB_GPIO);
//init the clock rate shadows
this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());