Merging USRP X300 and X310 support!!

6 files changed, 1322 insertions, 0 deletions

diff --git a/host/lib/transport/nirio/lvbitx/CMakeLists.txt b/host/lib/transport/nirio/lvbitx/CMakeLists.txt
new file mode 100644
index 000000000..35cfaa456
--- /dev/null
+++ b/host/lib/transport/nirio/lvbitx/CMakeLists.txt
@@ -0,0 +1,65 @@
+#
+# Copyright 2013 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+MACRO(LIBUHD_LVBITX_GEN_SOURCE_AND_BITSTREAM lvbitx binfile)
+    GET_FILENAME_COMPONENT(lvbitxprefix ${lvbitx} NAME_WE)
+
+    IF( ${binfile} STREQUAL "OFF" )
+        SET( GEN_OPTIONS )
+        MESSAGE( STATUS "  Using ${lvbitx} for codegen" )
+    ELSE( ${binfile} STREQUAL "OFF" )
+        SET( GEN_OPTIONS --merge-bin=${CMAKE_SOURCE_DIR}/../binaries/${binfile} --output-lvbitx-path=${CMAKE_SOURCE_DIR}/../binaries )
+        MESSAGE( STATUS "  Merging ${lvbitx} with ${binfile} for codegen" )
+    ENDIF( ${binfile} STREQUAL "OFF" )
+
+    SET(OUTPUT_PATH_OPT --output-src-path=${CMAKE_CURRENT_BINARY_DIR})
+    SET(IMAGES_PATH_OPT --uhd-images-path=${FPGA_IMAGES_DIR})
+
+    ADD_CUSTOM_COMMAND(
+        OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${lvbitxprefix}_lvbitx.hpp 
+        OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${lvbitxprefix}_lvbitx.cpp
+        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/process-lvbitx.py
+        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/template_lvbitx.hpp
+        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/template_lvbitx.cpp
+        DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/${lvbitx}
+        COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/process-lvbitx.py ${OUTPUT_PATH_OPT} ${IMAGES_PATH_OPT} ${GEN_OPTIONS} ${CMAKE_CURRENT_SOURCE_DIR}/${lvbitx}
+        COMMENT "Generating ${CMAKE_CURRENT_BINARY_DIR}/${lvbitxprefix}_lvbitx.cpp"
+    )
+
+    #make libuhd depend on the output file
+    LIBUHD_APPEND_SOURCES(${CMAKE_CURRENT_BINARY_DIR}/${lvbitxprefix}_lvbitx.cpp)
+ENDMACRO(LIBUHD_LVBITX_GEN_SOURCE_AND_BITSTREAM)
+
+INCLUDE_DIRECTORIES(${CMAKE_CURRENT_BINARY_DIR})
+
+########################################################################
+# Generation code
+########################################################################
+
+MESSAGE(STATUS "")
+MESSAGE(STATUS "Processing NI-RIO FPGA LVBITX Bitstreams...")
+
+FILE(TO_NATIVE_PATH ${CMAKE_INSTALL_PREFIX}/share/uhd/images default_images_dir)
+SET( FPGA_IMAGES_DIR ${default_images_dir} CACHE STRING "Path to installed FPGA image files." )
+OPTION( FPGA_IMAGES_DIR "Path to installed FPGA image files." "" )
+MESSAGE( STATUS "  LVBITX install directory: ${FPGA_IMAGES_DIR}" )
+
+# X300 Stuff
+LIBUHD_LVBITX_GEN_SOURCE_AND_BITSTREAM(x300.lvbitx_base OFF)
+
+# X310 Stuff
+LIBUHD_LVBITX_GEN_SOURCE_AND_BITSTREAM(x310.lvbitx_base OFF)
diff --git a/host/lib/transport/nirio/lvbitx/process-lvbitx.py b/host/lib/transport/nirio/lvbitx/process-lvbitx.py
new file mode 100755
index 000000000..a3d88d0bb
--- /dev/null
+++ b/host/lib/transport/nirio/lvbitx/process-lvbitx.py
@@ -0,0 +1,185 @@
+#!/usr/bin/python
+#
+# Copyright 2013-2014 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+from xml.etree import ElementTree
+from collections import namedtuple
+import optparse
+import base64
+import hashlib
+import os
+import sys
+
+# Parse options
+parser = optparse.OptionParser()
+parser.add_option("--uhd-images-path", type="string", dest="uhd_images_path", help="Install location for UHD images", default='')
+parser.add_option("--merge-bin", type="string", dest="merge_bin", help="Path to bin file that needs to be merged with the LVBITX before exporting", default=None)
+parser.add_option("--output-bin", action="store_true", dest="output_bin", help="Generate a binary FPGA programming bitstream file", default=False)
+parser.add_option("--output-lvbitx-path", type="string", dest="output_lvbitx_path", help="Output path for autogenerated LVBITX file", default=None)
+parser.add_option("--output-src-path", type="string", dest="output_src_path", help="Output path for autogenerated src file", default=None)
+(options, args) = parser.parse_args()
+
+# Args
+if (len(args) < 1):
+    print 'ERROR: Please specify the input LVBITX file name'
+    sys.exit(1)
+
+lvbitx_filename = args[0]
+input_filename = os.path.abspath(lvbitx_filename)
+autogen_src_path = os.path.abspath(options.output_src_path) if (options.output_src_path is not None) else os.path.dirname(input_filename)
+class_name = os.path.splitext(os.path.basename(input_filename))[0]
+
+if (not os.path.isfile(input_filename)):
+    print 'ERROR: FPGA File ' + input_filename + ' could not be accessed or is not a file.'
+    sys.exit(1)
+if (options.merge_bin is not None and not os.path.isfile(os.path.abspath(options.merge_bin))):
+    print 'ERROR: FPGA Bin File ' + options.merge_bin + ' could not be accessed or is not a file.'
+    sys.exit(1)
+if (not os.path.exists(autogen_src_path)):
+    print 'ERROR: Output path ' + autogen_src_path + ' could not be accessed.'
+    sys.exit(1)
+if (options.output_lvbitx_path is not None and input_filename == os.path.join(autogen_src_path, class_name + '.lvbitx')):
+    print 'ERROR: Input and output LVBITX files were the same. Choose a difference input file or output path.'
+    sys.exit(1)
+
+# Get XML Tree Node
+tree = ElementTree.parse(input_filename)
+root = tree.getroot()
+codegen_transform = {}
+
+# General info
+codegen_transform['autogen_msg'] = '// Auto-generated file: DO NOT EDIT!\n// Generated from a LabVIEW FPGA LVBITX image using "process-lvbitx.py"'
+codegen_transform['lvbitx_search_paths'] = options.uhd_images_path.replace('\\', '\\\\')
+codegen_transform['lvbitx_classname'] = class_name
+codegen_transform['lvbitx_classname_u'] = class_name.upper()
+bitstream_version = root.find('BitstreamVersion').text
+
+# Enumerate registers (controls and indicators)
+register_list = root.find('VI').find('RegisterList')
+
+reg_init_seq = ''
+control_list = ''
+indicator_list = ''
+control_idx = 0
+indicator_idx = 0
+for register in register_list.findall('Register'):
+    reg_type = 'INDICATOR' if (register.find('Indicator').text.lower() == 'true') else 'CONTROL'
+    reg_name = '\"' + register.find('Name').text + '\"'
+
+    if (reg_type == 'INDICATOR'):
+        indicator_list += '\n    ' + reg_name + ','
+        idx = indicator_idx
+        indicator_idx += 1
+    else:
+        control_list += '\n    ' + reg_name + ','
+        idx = control_idx
+        control_idx += 1
+
+    reg_init_seq += '\n    vtr.push_back(nirio_register_info_t('
+    reg_init_seq += hex(int(register.find('Offset').text)) + ', '
+    reg_init_seq += reg_type + 'S[' + str(idx) + '], '
+    reg_init_seq += reg_type
+    reg_init_seq += ')); //' + reg_name
+
+
+codegen_transform['register_init'] = reg_init_seq
+codegen_transform['control_list'] = control_list
+codegen_transform['indicator_list'] = indicator_list
+
+# Enumerate FIFOs
+nifpga_metadata = root.find('Project').find('CompilationResultsTree').find('CompilationResults').find('NiFpga')
+dma_channel_list = nifpga_metadata.find('DmaChannelAllocationList')
+reg_block_list = nifpga_metadata.find('RegisterBlockList')
+
+fifo_init_seq = ''
+out_fifo_list = ''
+in_fifo_list = ''
+out_fifo_idx = 0
+in_fifo_idx = 0
+for dma_channel in dma_channel_list:
+    fifo_name = '\"' + dma_channel.attrib['name'] + '\"'
+    direction = 'OUTPUT_FIFO' if (dma_channel.find('Direction').text == 'HostToTarget') else 'INPUT_FIFO'
+    for reg_block in reg_block_list.findall('RegisterBlock'):
+        if (reg_block.attrib['name'] == dma_channel.find('BaseAddressTag').text):
+            base_addr = reg_block.find('Offset').text
+            break
+
+    if (direction == 'OUTPUT_FIFO'):
+        out_fifo_list += '\n    ' + fifo_name + ','
+        idx = out_fifo_idx
+        out_fifo_idx += 1
+    else:
+        in_fifo_list += '\n    ' + fifo_name + ','
+        idx = in_fifo_idx
+        in_fifo_idx += 1
+
+    fifo_init_seq += '\n    vtr.push_back(nirio_fifo_info_t('
+    fifo_init_seq += dma_channel.find('Number').text + ', '
+    fifo_init_seq += direction + 'S[' + str(idx) + '], '
+    fifo_init_seq += direction + ', '
+    fifo_init_seq += str.lower(base_addr) + ', '
+    fifo_init_seq += dma_channel.find('NumberOfElements').text + ', '
+    fifo_init_seq += 'SCALAR_' + dma_channel.find('DataType').find('SubType').text + ', '
+    fifo_init_seq += dma_channel.find('DataType').find('WordLength').text + ', '
+    fifo_init_seq += bitstream_version
+    fifo_init_seq += ')); //' + fifo_name
+
+
+codegen_transform['fifo_init'] = fifo_init_seq
+codegen_transform['out_fifo_list'] = out_fifo_list
+codegen_transform['in_fifo_list'] = in_fifo_list
+
+# Merge bitstream into LVBITX
+if (options.merge_bin is not None):
+    with open(os.path.abspath(options.merge_bin), 'rb') as bin_file:
+        bitstream = bin_file.read()
+        bitstream_md5 = hashlib.md5(bitstream).hexdigest()
+        bitstream_b64 = base64.b64encode(bitstream)
+        bitstream_b64_lb = ''
+        for i in range(0, len(bitstream_b64), 76):
+            bitstream_b64_lb += bitstream_b64[i:i+76] + '\n'
+
+        root.find('Bitstream').text = bitstream_b64_lb
+        root.find('BitstreamMD5').text = bitstream_md5
+
+codegen_transform['lvbitx_signature'] = str.upper(root.find('SignatureRegister').text)
+
+# Write BIN file
+bitstream = base64.b64decode(root.find('Bitstream').text)
+if (options.output_lvbitx_path is not None and hashlib.md5(bitstream).hexdigest() != root.find('BitstreamMD5').text):
+    print 'ERROR: The MD5 sum for the output LVBITX was incorrect. Make sure that the bitstream in the input LVBITX or BIN file is valid.'
+    sys.exit(1)
+if (options.output_bin):
+    fpga_bin_file = open(os.path.join(options.output_lvbitx_path, class_name + '.bin'), 'w')
+    fpga_bin_file.write(bitstream)
+    fpga_bin_file.close()
+
+# Save LVBITX
+if (options.output_lvbitx_path is not None):
+    tree.write(os.path.join(options.output_lvbitx_path, class_name + '_fpga.lvbitx'), encoding="utf-8", xml_declaration=True, default_namespace=None, method="xml")
+
+# Save HPP and CPP
+with open(os.path.join(os.path.dirname(os.path.abspath(__file__)), 'template_lvbitx.hpp'), 'r') as template_file:
+    template_string = template_file.read()
+with open(os.path.join(autogen_src_path, class_name + '_lvbitx.hpp'), 'w') as source_file:
+    source_file.write(template_string.format(**codegen_transform))
+
+with open(os.path.join(os.path.dirname(os.path.abspath(__file__)), 'template_lvbitx.cpp'), 'r') as template_file:
+    template_string = template_file.read()
+with open(os.path.join(autogen_src_path, class_name + '_lvbitx.cpp'), 'w') as source_file:
+    source_file.write(template_string.format(**codegen_transform))
+
diff --git a/host/lib/transport/nirio/lvbitx/template_lvbitx.cpp b/host/lib/transport/nirio/lvbitx/template_lvbitx.cpp
new file mode 100644
index 000000000..a1899c771
--- /dev/null
+++ b/host/lib/transport/nirio/lvbitx/template_lvbitx.cpp
@@ -0,0 +1,86 @@
+{autogen_msg}
+
+#include "{lvbitx_classname}_lvbitx.hpp"
+#include <string>
+#include <iostream>
+#include <fstream>
+#include <streambuf>
+#include <boost/filesystem/path.hpp>
+#include <boost/algorithm/string.hpp>
+#include <boost/regex.hpp>
+
+namespace uhd {{ namespace niusrprio {{
+
+#define SEARCH_PATHS "{lvbitx_search_paths}"
+
+const char* {lvbitx_classname}_lvbitx::CONTROLS[] = {{{control_list}
+}};
+
+const char* {lvbitx_classname}_lvbitx::INDICATORS[] = {{{indicator_list}
+}};
+
+const char* {lvbitx_classname}_lvbitx::OUTPUT_FIFOS[] = {{{out_fifo_list}
+}};
+
+const char* {lvbitx_classname}_lvbitx::INPUT_FIFOS[] = {{{in_fifo_list}
+}};
+
+{lvbitx_classname}_lvbitx::{lvbitx_classname}_lvbitx(const std::string& option)
+{{
+    boost::filesystem::path fpga_path(_get_fpga_images_dir(SEARCH_PATHS));
+    fpga_path /= "usrp_{lvbitx_classname}_fpga_" + option + ".lvbitx";
+    _fpga_file_name = fpga_path.string();
+    _bitstream_checksum = _get_bitstream_checksum(_fpga_file_name);
+}}
+
+const char* {lvbitx_classname}_lvbitx::get_bitfile_path() {{
+    return _fpga_file_name.c_str();
+}}
+
+const char* {lvbitx_classname}_lvbitx::get_signature() {{
+    return "{lvbitx_signature}";
+}}
+
+const char* {lvbitx_classname}_lvbitx::get_bitstream_checksum() {{
+    return _bitstream_checksum.c_str();
+}}
+
+size_t {lvbitx_classname}_lvbitx::get_input_fifo_count() {{
+    return sizeof(INPUT_FIFOS)/sizeof(*INPUT_FIFOS);
+}}
+
+const char** {lvbitx_classname}_lvbitx::get_input_fifo_names() {{
+    return INPUT_FIFOS;
+}}
+
+size_t {lvbitx_classname}_lvbitx::get_output_fifo_count() {{
+    return sizeof(OUTPUT_FIFOS)/sizeof(*OUTPUT_FIFOS);
+}}
+
+const char** {lvbitx_classname}_lvbitx::get_output_fifo_names() {{
+    return OUTPUT_FIFOS;
+}}
+
+size_t {lvbitx_classname}_lvbitx::get_control_count() {{
+    return sizeof(CONTROLS)/sizeof(*CONTROLS);
+}}
+
+const char** {lvbitx_classname}_lvbitx::get_control_names() {{
+    return CONTROLS;
+}}
+
+size_t {lvbitx_classname}_lvbitx::get_indicator_count() {{
+    return sizeof(INDICATORS)/sizeof(*INDICATORS);
+}}
+
+const char** {lvbitx_classname}_lvbitx::get_indicator_names() {{
+    return INDICATORS;
+}}
+
+void {lvbitx_classname}_lvbitx::init_register_info(nirio_register_info_vtr& vtr) {{ {register_init}
+}}
+
+void {lvbitx_classname}_lvbitx::init_fifo_info(nirio_fifo_info_vtr& vtr) {{ {fifo_init}
+}}
+
+}}}}
diff --git a/host/lib/transport/nirio/lvbitx/template_lvbitx.hpp b/host/lib/transport/nirio/lvbitx/template_lvbitx.hpp
new file mode 100644
index 000000000..d8872e15c
--- /dev/null
+++ b/host/lib/transport/nirio/lvbitx/template_lvbitx.hpp
@@ -0,0 +1,48 @@
+{autogen_msg}
+
+#ifndef INCLUDED_{lvbitx_classname_u}_LVBITX_HPP
+#define INCLUDED_{lvbitx_classname_u}_LVBITX_HPP
+
+#include <uhd/transport/nirio/nifpga_lvbitx.h>
+
+namespace uhd {{ namespace niusrprio {{
+
+class {lvbitx_classname}_lvbitx : public nifpga_lvbitx {{
+public:
+    {lvbitx_classname}_lvbitx(const std::string& option);
+
+    virtual ~{lvbitx_classname}_lvbitx() {{}};
+
+    virtual const char* get_bitfile_path();
+    virtual const char* get_signature();
+    virtual const char* get_bitstream_checksum();
+
+    virtual size_t get_input_fifo_count();
+    virtual const char** get_input_fifo_names();
+
+    virtual size_t get_output_fifo_count();
+    virtual const char** get_output_fifo_names();
+
+    virtual size_t get_control_count();
+    virtual const char** get_control_names();
+
+    virtual size_t get_indicator_count();
+    virtual const char** get_indicator_names();
+
+    virtual void init_register_info(nirio_register_info_vtr& vtr);
+    virtual void init_fifo_info(nirio_fifo_info_vtr& vtr);
+
+    static const char* CONTROLS[];
+    static const char* INDICATORS[];
+    static const char* OUTPUT_FIFOS[];
+    static const char* INPUT_FIFOS[];
+
+private:
+    std::string _fpga_file_name;
+    std::string _bitstream_checksum;
+}};
+
+}}}}
+
+#endif /* INCLUDED_{lvbitx_classname_u}_LVBITX_HPP */
+
diff --git a/host/lib/transport/nirio/lvbitx/x300.lvbitx_base b/host/lib/transport/nirio/lvbitx/x300.lvbitx_base
new file mode 100755
index 000000000..c264e7157
--- /dev/null
+++ b/host/lib/transport/nirio/lvbitx/x300.lvbitx_base
@@ -0,0 +1,469 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Bitfile>
+  <BitfileVersion>4.0</BitfileVersion>
+  <Documentation>
+    <BuildSpecVersion/>
+    <BuildSpecDescription/>
+  </Documentation>
+  <SignatureRegister>97C6D9F4F4829001B83378F93CAB0C94</SignatureRegister>
+  <SignatureGuids>7BAD6AEB9741248079F13147B3F8AD94</SignatureGuids>
+  <SignatureNames>AE54C47F787D92DB46F7DC973338D786</SignatureNames>
+  <TimeStamp/>
+  <CompilationStatus/>
+  <BitstreamVersion>2</BitstreamVersion>
+  <VI>
+    <Name>USRP_X3x0_Top.vi</Name>
+    <RegisterList>
+      <Register>
+        <Name>ViSignature</Name>
+        <Hidden>true</Hidden>
+        <Indicator>true</Indicator>
+        <Datatype>
+          <Array>
+            <Name/>
+            <Size>4</Size>
+            <Type>
+              <U32>
+                <Name/>
+              </U32>
+            </Type>
+          </Array>
+        </Datatype>
+        <FlattenedType/>
+        <Grouping/>
+        <Offset>262132</Offset>
+        <SizeInBits>128</SizeInBits>
+        <Class>0</Class>
+        <Internal>true</Internal>
+        <TypedefPath/>
+        <TypedefRelativePath/>
+        <ID>0</ID>
+        <Bidirectional>false</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>DiagramReset</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
+          <U32>
+            <Name/>
+          </U32>
+        </Datatype>
+        <FlattenedType/>
+        <Grouping/>
+        <Offset>262140</Offset>
+        <SizeInBits>32</SizeInBits>
+        <Class>0</Class>
+        <Internal>true</Internal>
+        <TypedefPath/>
+        <TypedefRelativePath/>
+        <ID>0</ID>
+        <Bidirectional>true</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>ViControl</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
+          <U32>
+            <Name/>
+          </U32>
+        </Datatype>
+        <FlattenedType/>
+        <Grouping/>
+        <Offset>262136</Offset>
+        <SizeInBits>32</SizeInBits>
+        <Class>0</Class>
+        <Internal>true</Internal>
+        <TypedefPath/>
+        <TypedefRelativePath/>
+        <ID>0</ID>
+        <Bidirectional>true</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>InterruptEnable</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
+          <U32>
+            <Name/>
+          </U32>
+        </Datatype>
+        <FlattenedType/>
+        <Grouping/>
+        <Offset>262116</Offset>
+        <SizeInBits>32</SizeInBits>
+        <Class>0</Class>
+        <Internal>true</Internal>
+        <TypedefPath/>
+        <TypedefRelativePath/>
+        <ID>0</ID>
+        <Bidirectional>true</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>InterruptMask</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
+          <U32>
+            <Name/>
+          </U32>
+        </Datatype>
+        <FlattenedType/>
+        <Grouping/>
+        <Offset>262124</Offset>
+        <SizeInBits>32</SizeInBits>
+        <Class>0</Class>
+        <Internal>true</Internal>
+        <TypedefPath/>
+        <TypedefRelativePath/>
+        <ID>0</ID>
+        <Bidirectional>true</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>InterruptStatus</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
+          <U32>
+            <Name/>
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+              <UserVisible>true</UserVisible>
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+          </DmaChannelAllocationList>
+          <RegisterBlockList>
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+              <Offset>0xFCC0</Offset>
+            </RegisterBlock>
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+          <UsedBaseClockList>
+            <BaseClock name="ReliableClkIn">
+         </BaseClock>
+            <BaseClock name="ChinchClk">
+         </BaseClock>
+            <BaseClock name="40 MHz Onboard Clock">
+         </BaseClock>
+          </UsedBaseClockList>
+          <version>1</version>
+        </NiFpga>
+      </CompilationResults>
+    </CompilationResultsTree>
+    <MultipleUserClocks>false</MultipleUserClocks>
+    <AllowImplicitEnableRemoval>false</AllowImplicitEnableRemoval>
+  </Project>
+  <ClientData/>
+  <BitstreamMD5>a72ba1716893a0bd02f88dac3ab28e1b</BitstreamMD5>
+  <Bitstream>a72ba1716893a0bd02f88dac3ab28e1b</Bitstream>
+</Bitfile>
diff --git a/host/lib/transport/nirio/lvbitx/x310.lvbitx_base b/host/lib/transport/nirio/lvbitx/x310.lvbitx_base
new file mode 100755
index 000000000..c264e7157
--- /dev/null
+++ b/host/lib/transport/nirio/lvbitx/x310.lvbitx_base
@@ -0,0 +1,469 @@
+<?xml version="1.0" encoding="utf-8"?>
+<Bitfile>
+  <BitfileVersion>4.0</BitfileVersion>
+  <Documentation>
+    <BuildSpecVersion/>
+    <BuildSpecDescription/>
+  </Documentation>
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+  <SignatureGuids>7BAD6AEB9741248079F13147B3F8AD94</SignatureGuids>
+  <SignatureNames>AE54C47F787D92DB46F7DC973338D786</SignatureNames>
+  <TimeStamp/>
+  <CompilationStatus/>
+  <BitstreamVersion>2</BitstreamVersion>
+  <VI>
+    <Name>USRP_X3x0_Top.vi</Name>
+    <RegisterList>
+      <Register>
+        <Name>ViSignature</Name>
+        <Hidden>true</Hidden>
+        <Indicator>true</Indicator>
+        <Datatype>
+          <Array>
+            <Name/>
+            <Size>4</Size>
+            <Type>
+              <U32>
+                <Name/>
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+        <Internal>true</Internal>
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+        <TypedefRelativePath/>
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+        <Bidirectional>false</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>DiagramReset</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
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+            <Name/>
+          </U32>
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+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
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+        <Name>ViControl</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
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+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
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+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
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+        <Bidirectional>true</Bidirectional>
+        <Synchronous>false</Synchronous>
+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
+      </Register>
+      <Register>
+        <Name>InterruptMask</Name>
+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
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+            <Name/>
+          </U32>
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+        <Bidirectional>true</Bidirectional>
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+        <MechanicalAction>Switch When Pressed</MechanicalAction>
+        <AccessMayTimeout>false</AccessMayTimeout>
+        <RegisterNode>false</RegisterNode>
+        <SubControlList/>
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+        <Hidden>false</Hidden>
+        <Indicator>false</Indicator>
+        <Datatype>
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+        <Bidirectional>true</Bidirectional>
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+        <AccessMayTimeout>false</AccessMayTimeout>
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+        <SubControlList/>
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+    <AutoRunWhenDownloaded>false</AutoRunWhenDownloaded>
+    <CompilationResultsTree>
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+              <Implementation>niFpgaTargetToHost</Implementation>
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+              <UserVisible>true</UserVisible>
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+            <Channel name="RX FIFO 5">
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+              <Implementation>niFpgaTargetToHost</Implementation>
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+              <NumberOfElements>1023</NumberOfElements>
+              <UserVisible>true</UserVisible>
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+            <Channel name="TX FIFO 0">
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+              <Direction>HostToTarget</Direction>
+              <Implementation>niFpgaHostToTarget</Implementation>
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+              <NumberOfElements>1029</NumberOfElements>
+              <UserVisible>true</UserVisible>
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+            <Channel name="TX FIFO 1">
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+              <Implementation>niFpgaHostToTarget</Implementation>
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+              <NumberOfElements>1029</NumberOfElements>
+              <UserVisible>true</UserVisible>
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+              <NumberOfElements>1029</NumberOfElements>
+              <UserVisible>true</UserVisible>
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+            <Channel name="TX FIFO 4">
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+              <Implementation>niFpgaHostToTarget</Implementation>
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+              <UserVisible>true</UserVisible>
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+            <Channel name="TX FIFO 5">
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+                <Signed>false</Signed>
+                <SubType>U64</SubType>
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+              <Direction>HostToTarget</Direction>
+              <Implementation>niFpgaHostToTarget</Implementation>
+              <Number>11</Number>
+              <NumberOfElements>1029</NumberOfElements>
+              <UserVisible>true</UserVisible>
+            </Channel>
+          </DmaChannelAllocationList>
+          <RegisterBlockList>
+            <RegisterBlock name="NiLvFpgaFIFO 0">
+              <Offset>0xFF80</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 1">
+              <Offset>0xFF40</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 2">
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+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 3">
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+            <RegisterBlock name="NiLvFpgaFIFO 4">
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+            <RegisterBlock name="NiLvFpgaFIFO 5">
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+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 6">
+              <Offset>0xFE00</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 7">
+              <Offset>0xFDC0</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 8">
+              <Offset>0xFD80</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 9">
+              <Offset>0xFD40</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 10">
+              <Offset>0xFD00</Offset>
+            </RegisterBlock>
+            <RegisterBlock name="NiLvFpgaFIFO 11">
+              <Offset>0xFCC0</Offset>
+            </RegisterBlock>
+          </RegisterBlockList>
+          <UsedBaseClockList>
+            <BaseClock name="ReliableClkIn">
+         </BaseClock>
+            <BaseClock name="ChinchClk">
+         </BaseClock>
+            <BaseClock name="40 MHz Onboard Clock">
+         </BaseClock>
+          </UsedBaseClockList>
+          <version>1</version>
+        </NiFpga>
+      </CompilationResults>
+    </CompilationResultsTree>
+    <MultipleUserClocks>false</MultipleUserClocks>
+    <AllowImplicitEnableRemoval>false</AllowImplicitEnableRemoval>
+  </Project>
+  <ClientData/>
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