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| author | mattprost <matt.prost@ni.com> | 2020-09-02 18:57:01 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-09-03 15:02:05 -0500 |
| commit | d80d56114a5eb15b844afc17b9962f0cf4b4ca28 (patch) | |
| tree | 1042b502d3f032eb191abd31856405992b46e70d /host/lib/include | |
| parent | 148a2c5ee69ad9c2576d4005b01c739de1261fe4 (diff) | |
| download | uhd-d80d56114a5eb15b844afc17b9962f0cf4b4ca28.tar.gz uhd-d80d56114a5eb15b844afc17b9962f0cf4b4ca28.tar.bz2 uhd-d80d56114a5eb15b844afc17b9962f0cf4b4ca28.zip | |
twinrx: Bypass adf535x feedback divider
Bypass the LO1 feedback divider if it is not required. Some TwinRX units
have seen issues when tuning to frequencies between 3.5GHz and 5.1GHz
while following that data path.
Signed-off-by: mattprost <matt.prost@ni.com>
Diffstat (limited to 'host/lib/include')
| -rw-r--r-- | host/lib/include/uhdlib/usrp/common/adf535x.hpp | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/host/lib/include/uhdlib/usrp/common/adf535x.hpp b/host/lib/include/uhdlib/usrp/common/adf535x.hpp index 03efecc36..736018da1 100644 --- a/host/lib/include/uhdlib/usrp/common/adf535x.hpp +++ b/host/lib/include/uhdlib/usrp/common/adf535x.hpp @@ -140,12 +140,6 @@ public: void set_feedback_select(const feedback_sel_t fb_sel) override { _fb_after_divider = (fb_sel == FB_SEL_DIVIDED); - - if (_fb_after_divider) { - _regs.feedback_select = adf535x_regs_t::FEEDBACK_SELECT_DIVIDED; - } else { - _regs.feedback_select = adf535x_regs_t::FEEDBACK_SELECT_FUNDAMENTAL; - } } void set_pfd_freq(const double pfd_freq) override @@ -359,7 +353,7 @@ private: // Members uint32_t _wait_time_us; double _ref_freq; double _pfd_freq; - double _fb_after_divider; + bool _fb_after_divider; }; // ADF5355 Functions @@ -451,6 +445,12 @@ inline double adf535x_impl<adf5355_regs_t>::_set_frequency( % FRAC1 % MOD2 % FRAC2); /* Update registers */ + if ((rf_divider == 1) or not _fb_after_divider) { + _regs.feedback_select = adf5355_regs_t::FEEDBACK_SELECT_FUNDAMENTAL; + } + else { + _regs.feedback_select = adf5355_regs_t::FEEDBACK_SELECT_DIVIDED; + } _regs.int_16_bit = INT; _regs.frac1_24_bit = FRAC1; _regs.frac2_14_bit = FRAC2; @@ -588,6 +588,12 @@ inline double adf535x_impl<adf5356_regs_t>::_set_frequency( % FRAC1 % MOD2 % FRAC2); /* Update registers */ + if ((rf_divider == 1) or not _fb_after_divider) { + _regs.feedback_select = adf5356_regs_t::FEEDBACK_SELECT_FUNDAMENTAL; + } + else { + _regs.feedback_select = adf5356_regs_t::FEEDBACK_SELECT_DIVIDED; + } _regs.int_16_bit = INT; _regs.frac1_24_bit = FRAC1; _regs.frac2_lsb = narrow_cast<uint16_t>(FRAC2 & 0x3FFF); |