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authorPaul David <paul.david@ettus.com>2016-09-29 14:36:04 -0700
committermbr0wn <martin.braun@ettus.com>2016-10-05 14:31:53 -0700
commited3be5607de7ea20f3ed1a5bfef4a060ade006be (patch)
treea5ec90c7d18bd91eb63fbe566d0980f15e8705df /host/lib/ic_reg_maps
parent93990d78520848d00e586d6bae10048c36d2ea89 (diff)
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max2871: Added label for the bit region VAS_DLY
- Also added a template specialization for enabling the VAS_DLY bit locations based on VAS_TEMP setting (aka retune)
Diffstat (limited to 'host/lib/ic_reg_maps')
-rwxr-xr-xhost/lib/ic_reg_maps/gen_max2871_regs.py5
1 files changed, 4 insertions, 1 deletions
diff --git a/host/lib/ic_reg_maps/gen_max2871_regs.py b/host/lib/ic_reg_maps/gen_max2871_regs.py
index f591c1636..f500d8aa8 100755
--- a/host/lib/ic_reg_maps/gen_max2871_regs.py
+++ b/host/lib/ic_reg_maps/gen_max2871_regs.py
@@ -74,6 +74,7 @@ counter_reset 0x02[3] 0 normal, reset
vco 0x03[26:31] 0
## VCO autoselect
shutdown_vas 0x03[25] 0 enabled, disabled
+## should actually be called vas_temp ...
retune 0x03[24] 1 disabled, enabled
res3 0x3[19:23] 0
csm 0x3[18] 0 disabled, enabled
@@ -107,7 +108,9 @@ output_power 0x04[3:4] 3 m4dBm, m1dBm, 2dBm, 5dBm
## Misc
## Write only, default = 0x18400005
########################################################################
-res5_26_31 0x05[26:31] 0x18
+res5_31 0x05[31] 0
+vas_dly 0x05[29:30] 3 disabled, res0, res1, enabled
+res5_26_28 0x05[26:28] 0
shutdown_pll 0x05[25] 0 enabled, disabled
f01 0x05[24] 1 frac_n, auto
ld_pin_mode 0x05[22:23] 1 low, dld, ald, high