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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-06-25 19:43:16 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-01 17:07:58 -0700 |
| commit | e59ce9d103278f1bb269a0ed163163488b697419 (patch) | |
| tree | 550b76078a877bcb37a547d1e5eba48afb087390 /host/lib/ic_reg_maps | |
| parent | cfb304d1cc5cb7b219f686eca5e2a5bb80d7e5ea (diff) | |
| download | uhd-e59ce9d103278f1bb269a0ed163163488b697419.tar.gz uhd-e59ce9d103278f1bb269a0ed163163488b697419.tar.bz2 uhd-e59ce9d103278f1bb269a0ed163163488b697419.zip | |
x300: Added set/get_clock_delay to x300_clock_ctrl
- This function allows delaying divider pairs using the digital and analog
delay blocks in the LMK divider
- ctrl object caches delay for later retrieval
- Minor fixes to LMK regmap
Diffstat (limited to 'host/lib/ic_reg_maps')
| -rw-r--r-- | host/lib/ic_reg_maps/gen_lmk04816_regs.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/ic_reg_maps/gen_lmk04816_regs.py b/host/lib/ic_reg_maps/gen_lmk04816_regs.py index e89a82671..d1f0633a4 100644 --- a/host/lib/ic_reg_maps/gen_lmk04816_regs.py +++ b/host/lib/ic_reg_maps/gen_lmk04816_regs.py @@ -26,7 +26,7 @@ address0 0[0:4] 0 CLKout0_1_DIV 0[5:15] 25 CLKout0_1_HS 0[16] 0 RESET 0[17] 0 no_reset, reset -CLKout0_1_DDLY 0[18:27] 0 five +CLKout0_1_DDLY 0[18:27] 0 CLKout0_ADLY_SEL 0[28] 0 d_pd, d_ev_x, d_odd_y, d_both CLKout1_ADLY_SEL 0[29] 0 d_pd, d_ev_x, d_odd_y, d_both Required_0 0[30] 0 |