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authorTrung N Tran <trung.tran@ettus.com>2017-11-29 17:47:10 -0800
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:05:57 -0800
commitde7ed3081b6b9746c320669d87d318e82e4af7f4 (patch)
tree26c926af167b62e8d66c764ffd1cee0eafd5fb49 /host/lib/ic_reg_maps
parent8bccbf85643feb7e88b768e41f29cc5aa66e2aa2 (diff)
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mg: Fix TX power issues
- Fixed incorrect register address for channel 1 lowband mixer select - Fixed enabling of bypass path
Diffstat (limited to 'host/lib/ic_reg_maps')
-rw-r--r--host/lib/ic_reg_maps/gen_mgcpld_regs.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/ic_reg_maps/gen_mgcpld_regs.py b/host/lib/ic_reg_maps/gen_mgcpld_regs.py
index fd3d9673f..c42e1a5a3 100644
--- a/host/lib/ic_reg_maps/gen_mgcpld_regs.py
+++ b/host/lib/ic_reg_maps/gen_mgcpld_regs.py
@@ -42,7 +42,7 @@ ch1_idle_rx_myk_en 0x0052[10] 0
ch1_on_tx_sw1 0x0053[0:1] 0 ShutdownTxSw1,FromTxFilterLp1700MHz,FromTxFilterLp3400MHz,FromTxFilterLp0800MHz
ch1_on_tx_sw2 0x0053[2:5] 1 ToTxFilterLp3400MHz=1,ToTxFilterLp1700MHz=2,ToTxFilterLp0800MHz=4,ToTxFilterLp6400MHz=8
ch1_on_tx_sw3 0x0053[6] 0 ToTxFilterBanks,BypassPathToTrxSw
-ch1_on_tx_lowband_mixer_path_select 0x0050[7] 0 bypass,enable
+ch1_on_tx_lowband_mixer_path_select 0x0053[7] 0 bypass,enable
ch1_on_tx_mixer_en 0x0053[8] 0
ch1_on_tx_amp_en 0x0053[9] 0
ch1_on_tx_pa_en 0x0053[10] 0
@@ -90,7 +90,7 @@ ch2_idle_rx_myk_en 0x0062[10] 0
ch2_on_tx_sw1 0x0063[0:1] 0 ShutdownTxSw1,FromTxFilterLp1700MHz,FromTxFilterLp3400MHz,FromTxFilterLp0800MHz
ch2_on_tx_sw2 0x0063[2:5] 1 ToTxFilterLp3400MHz=1,ToTxFilterLp1700MHz=2,ToTxFilterLp0800MHz=4,ToTxFilterLp6400MHz=8
ch2_on_tx_sw3 0x0063[6] 0 ToTxFilterBanks,BypassPathToTrxSw
-ch2_on_tx_lowband_mixer_path_select 0x0050[7] 0 bypass,enable
+ch2_on_tx_lowband_mixer_path_select 0x0063[7] 0 bypass,enable
ch2_on_tx_mixer_en 0x0063[8] 0
ch2_on_tx_amp_en 0x0063[9] 0
ch2_on_tx_pa_en 0x0063[10] 0