Moved a bunch of register map code into common.

1 files changed, 53 insertions, 2 deletions

diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py
index b33961b03..4aa1ef35e 100644
--- a/host/lib/ic_reg_maps/common.py
+++ b/host/lib/ic_reg_maps/common.py
@@ -16,9 +16,48 @@
 #
 
 import re
+import sys
 import math
 from Cheetah.Template import Template
 
+COMMON_TMPL = """\
+#import time
+/***********************************************************************
+ * This file was generated by $file on $time.strftime("%c")
+ **********************************************************************/
+
+\#ifndef INCLUDED_$(name.upper())_HPP
+\#define INCLUDED_$(name.upper())_HPP
+
+\#include <boost/cstdint.hpp>
+
+struct $(name)_t{
+
+    #for $reg in $regs
+        #if $reg.get_enums()
+    enum $reg.get_type(){
+        #for $i, $enum in enumerate($reg.get_enums())
+        #set $end_comma = ',' if $i < len($reg.get_enums())-1 else ''
+        $(reg.get_name().upper())_$(enum[0].upper()) = $enum[1]$end_comma
+        #end for
+    };
+        #end if
+    $reg.get_type() $reg.get_name();
+    #end for
+
+    $(name)_t(void){
+    #for $reg in $regs
+        $reg.get_name() = $reg.get_default();
+    #end for
+    }
+
+$body
+
+};
+
+\#endif /* INCLUDED_$(name.upper())_HPP */
+"""
+
 def parse_tmpl(_tmpl_text, **kwargs):
     return str(Template(_tmpl_text, kwargs))
 
@@ -60,8 +99,20 @@ class reg:
         for key, val in self.get_enums():
             if val == self._default: return str.upper('%s_%s'%(self.get_name(), key))
         return self._default
-    def get_stdint_type(self):\
-        return 'uint%d_t'%max(2**math.ceil(math.log(self.get_bit_width(), 2)), 8)
+    def get_type(self):
+        if self.get_enums(): return '%s_t'%self.get_name()
+        return 'boost::uint%d_t'%max(2**math.ceil(math.log(self.get_bit_width(), 2)), 8)
     def get_shift(self): return self._addr_spec[0]
     def get_mask(self): return hex(int('1'*self.get_bit_width(), 2))
     def get_bit_width(self): return self._addr_spec[1] - self._addr_spec[0] + 1
+
+def generate(name, regs_tmpl, body_tmpl='', file=__file__):
+    regs = map(reg, parse_tmpl(regs_tmpl).splitlines())
+    body = parse_tmpl(body_tmpl, regs=regs).replace('\n', '\n    ').strip()
+    code = parse_tmpl(COMMON_TMPL,
+        name=name,
+        regs=regs,
+        body=body,
+        file=file,
+    )
+    open(sys.argv[1], 'w').write(code)