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authorWade Fife <wade.fife@ettus.com>2020-06-16 11:31:45 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2020-06-29 14:03:17 -0500
commitcf82b36388880237fe7b690c16dde46afc1a3da3 (patch)
tree8e3812e5b2229c1030457a25815a668cb79ea108 /host/include
parent1cef9d62d698a7cc33f936ab3df32e6dcd933487 (diff)
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fpga: rfnoc: Add Log-Power block
Diffstat (limited to 'host/include')
-rw-r--r--host/include/uhd/rfnoc/blocks/logpwr.yml56
1 files changed, 56 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/blocks/logpwr.yml b/host/include/uhd/rfnoc/blocks/logpwr.yml
new file mode 100644
index 000000000..c1350c627
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/logpwr.yml
@@ -0,0 +1,56 @@
+schema: rfnoc_modtool_args
+module_name: logpwr
+version: 1.0
+rfnoc_version: 1.0
+chdr_width: 64
+noc_id: 0x4C500000
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_logpwr/Makefile.srcs"
+
+parameters:
+ NUM_PORTS: 1
+ RANDOM_MODE: 2'b11
+
+clocks:
+ - name: rfnoc_chdr
+ freq: "[]"
+ - name: rfnoc_ctrl
+ freq: "[]"
+ - name: ce
+ freq: "[]"
+
+control:
+ sw_iface: nocscript
+ fpga_iface: ctrlport
+ interface_direction: slave
+ fifo_depth: 32
+ clk_domain: ce
+ ctrlport:
+ byte_mode: False
+ timed: False
+ has_status: False
+
+data:
+ fpga_iface: axis_pyld_ctxt
+ clk_domain: ce
+ inputs:
+ in:
+ num_ports: NUM_PORTS
+ item_width: 32
+ nipc: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 32
+ format: sc16
+ mdata_sig: ~
+ outputs:
+ out:
+ num_ports: NUM_PORTS
+ item_width: 16
+ nipc: 1
+ context_fifo_depth: 2
+ payload_fifo_depth: 32
+ format: s16
+ mdata_sig: ~
+
+registers:
+
+properties: