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| author | djepson1 <daniel.jepson@ni.com> | 2017-10-09 11:26:20 -0500 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:04:02 -0800 |
| commit | 4e0600b00a053b23dadd02ac99d89db9d50e1f34 (patch) | |
| tree | 0cabfacab9bc9494000a0a57d8ac4109f8aafc83 /host/include | |
| parent | 6858b05357c8d5a84334d06d1b7ccf607deb42d3 (diff) | |
| download | uhd-4e0600b00a053b23dadd02ac99d89db9d50e1f34.tar.gz uhd-4e0600b00a053b23dadd02ac99d89db9d50e1f34.tar.bz2 uhd-4e0600b00a053b23dadd02ac99d89db9d50e1f34.zip | |
mg: Updated JESD204b init seq and documentation.
- Based on feedback from ADI, updated SYSREF sequencing for
meeting deterministic latency requirements.
- Changed majority of register addresses in nijesdcore.py to
constants.
- Corrected write data to SYSREF_CAPTURE_CONTROL to produce
the correct SYSREF toggle rate inside the FPGA.
Signed-off-by: djepson1 <daniel.jepson@ni.com>
Diffstat (limited to 'host/include')
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