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| author | Michael West <michael.west@ettus.com> | 2020-03-15 01:17:50 -0700 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-05-12 12:03:31 -0500 |
| commit | 12dfb97c8efce40494efb35bdd81d06b6f8b9b62 (patch) | |
| tree | 7a5e7f12425dd6a3c5fbb9e2b2ff7faf3a276482 /host/include | |
| parent | 7886b71f13e9f6e5786c95286ef98f49ab716119 (diff) | |
| download | uhd-12dfb97c8efce40494efb35bdd81d06b6f8b9b62.tar.gz uhd-12dfb97c8efce40494efb35bdd81d06b6f8b9b62.tar.bz2 uhd-12dfb97c8efce40494efb35bdd81d06b6f8b9b62.zip | |
DUC/DDC: Add variable time increment
Sets time increment based on tick rate and sample rate instead of
assuming one tick per sample. Defaults to legacy behavior.
Minor compat number bumped on DUC and DDC blocks.
Signed-off-by: Michael West <michael.west@ettus.com>
Diffstat (limited to 'host/include')
| -rw-r--r-- | host/include/uhd/rfnoc/ddc_block_control.hpp | 1 | ||||
| -rw-r--r-- | host/include/uhd/rfnoc/duc_block_control.hpp | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/ddc_block_control.hpp b/host/include/uhd/rfnoc/ddc_block_control.hpp index f4197dd55..834fa0aa3 100644 --- a/host/include/uhd/rfnoc/ddc_block_control.hpp +++ b/host/include/uhd/rfnoc/ddc_block_control.hpp @@ -46,6 +46,7 @@ public: static const uint32_t SR_DECIM_ADDR; static const uint32_t SR_MUX_ADDR; static const uint32_t SR_COEFFS_ADDR; + static const uint32_t SR_TIME_INCR_ADDR; /*! Set the DDS frequency * diff --git a/host/include/uhd/rfnoc/duc_block_control.hpp b/host/include/uhd/rfnoc/duc_block_control.hpp index 4cf8a8fb8..cf9d3a5d7 100644 --- a/host/include/uhd/rfnoc/duc_block_control.hpp +++ b/host/include/uhd/rfnoc/duc_block_control.hpp @@ -45,6 +45,7 @@ public: static const uint32_t SR_FREQ_ADDR; static const uint32_t SR_SCALE_IQ_ADDR; static const uint32_t SR_INTERP_ADDR; + static const uint32_t SR_TIME_INCR_ADDR; /*! Set the DDS frequency * |