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| author | Sugandha Gupta <sugandha.gupta@ettus.com> | 2019-10-15 11:52:46 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2019-11-26 12:21:32 -0800 |
| commit | a801d6b046743140e9a50c7788dd17dd71f5540a (patch) | |
| tree | 58d164e1b4cb2a8d871ca532287699f3912ae3d8 /host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile | |
| parent | 2a7e69d862f661075b98bab19e58d958c28a9af8 (diff) | |
| download | uhd-a801d6b046743140e9a50c7788dd17dd71f5540a.tar.gz uhd-a801d6b046743140e9a50c7788dd17dd71f5540a.tar.bz2 uhd-a801d6b046743140e9a50c7788dd17dd71f5540a.zip | |
examples: Add example out-of-tree module for RFNoC modules
This subdirectory is its own, self-contained project. It is supposed to
work against the UHD version it is shipped with.
Co-Authored-By: Martin Braun <martin.braun@ettus.com>
Co-Authored-By: Wade Fife <wade.fife@ni.com>
Diffstat (limited to 'host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile')
| -rw-r--r-- | host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile new file mode 100644 index 000000000..1ff3046ee --- /dev/null +++ b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile @@ -0,0 +1,47 @@ +# +# Copyright 2019 Ettus Research, A National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir. Note: +# UHD_FPGA_DIR must be passed into this Makefile. +ifndef UHD_FPGA_DIR +$(error "UHD_FPGA_DIR is not set! Must point to UHD FPGA repository!") +endif +BASE_DIR = $(UHD_FPGA_DIR)/usrp3/top +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its +# dependencies. +include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include Makefile.srcs + +DESIGN_SRCS += $(abspath \ +$(RFNOC_CORE_SRCS) \ +$(RFNOC_UTIL_SRCS) \ +$(RFNOC_OOT_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +SIM_TOP = rfnoc_block_gain_tb +SIM_SRCS = \ +$(abspath rfnoc_block_gain_tb.sv) \ + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |