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author | Josh Blum <josh@joshknows.com> | 2011-05-03 16:55:27 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-05-03 16:55:27 -0700 |
commit | 4e0b42afcbbf1067cef2ad530f3b162e5a35771b (patch) | |
tree | 708547b217482a6404f2c75ad7ab19a69a74dc9e /host/docs | |
parent | e75919bc9e1cb1b5f8f69b5a5aabed9b3a1a53d9 (diff) | |
parent | b4fc0d61bb6cbd1a5614745bab9aeb0abc22cb6f (diff) | |
download | uhd-4e0b42afcbbf1067cef2ad530f3b162e5a35771b.tar.gz uhd-4e0b42afcbbf1067cef2ad530f3b162e5a35771b.tar.bz2 uhd-4e0b42afcbbf1067cef2ad530f3b162e5a35771b.zip |
Merge branch 'master' into next
Diffstat (limited to 'host/docs')
-rw-r--r-- | host/docs/dboards.rst | 40 | ||||
-rw-r--r-- | host/docs/usrp1.rst | 9 | ||||
-rw-r--r-- | host/docs/usrp_e1xx.rst | 16 |
3 files changed, 58 insertions, 7 deletions
diff --git a/host/docs/dboards.rst b/host/docs/dboards.rst index 373189441..42965b32f 100644 --- a/host/docs/dboards.rst +++ b/host/docs/dboards.rst @@ -130,6 +130,7 @@ Bandwidths (Hz): Sensors: * **lo_locked**: boolean for LO lock state +* **rssi**: float for rssi in dBm ^^^^^^^^^^^^^^^^^^^^^^^^^^^ XCVR 2450 @@ -204,6 +205,45 @@ Sensors: * **lo_locked**: boolean for LO lock state ^^^^^^^^^^^^^^^^^^^^^^^^^^^ +SBX Series +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +The SBX Series boards have 2 quadrature subdevices, one transmit, one receive. +Transmit and Receive default to direct conversion but +can be used in low IF mode through lo_offset in uhd::tune_request_t + +The SBX Series boards have independent receive and transmit LO's and synthesizers +allowing full-duplex operation on different transmit and receive frequencies. + +Transmit Antennas: **TX/RX** + +Receive Antennas: **TX/RX** or **RX2** + +The user may set the receive antenna to be TX/RX or RX2. +However, when using an SBX board in full-duplex mode, +the receive antenna will always be set to RX2, regardless of the settings. + +Transmit Gains: **PGA0**, Range: 0-31.5dB + +Receive Gains: **PGA0**, Range: 0-31.5dB + +Bandwidths (Hz): + +* **RX**: 40M +* **TX**: 40M + +Sensors: + +* **lo_locked**: boolean for LO lock state + +LEDs: + +* All LEDs flash when dboard control is initialized +* **TX LD**: Transmit Synthesizer Lock Detect +* **TX/RX**: Receiver on TX/RX antenna port (No TX) +* **RX LD**: Receive Synthesizer Lock Detect +* **RX1/RX2**: Receiver on RX2 antenna port + +^^^^^^^^^^^^^^^^^^^^^^^^^^^ TVRX ^^^^^^^^^^^^^^^^^^^^^^^^^^^ The TVRX board has 1 real-mode subdevice. diff --git a/host/docs/usrp1.rst b/host/docs/usrp1.rst index f77a26e0a..97a8c3bb5 100644 --- a/host/docs/usrp1.rst +++ b/host/docs/usrp1.rst @@ -136,6 +136,11 @@ The USRP can be modified to accept an external clock reference instead of the 64 The new external clock needs to be a square wave between +7dBm and +15dBm -For the correct clock settings, call usrp->set_master_clock_rate(EXT_CLOCK_FREQUENCY) -before any other parameters are set in your application. +After the hardware modification, +the user should burn the setting into the EEPROM, +so UHD can initialize with the correct clock rate. +Run the following commands to record the setting into the EEPROM: +:: + cd <install-path>/share/uhd/utils + ./usrp_burn_mb_eeprom --args=<optional device args> --key=mcr --val=<rate> diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1xx.rst index 2818a0a65..036d2c02c 100644 --- a/host/docs/usrp_e1xx.rst +++ b/host/docs/usrp_e1xx.rst @@ -20,7 +20,6 @@ Example device address string representations to specify non-standard FPGA image Changing the master clock rate ------------------------------------------------------------------------ The master clock rate of the USRP embedded feeds both the FPGA DSP and the codec chip. -UHD can dynamically reconfigure the clock rate though the set_master_clock_rate() API call. Hundreds of rates between 32MHz and 64MHz are available. A few notable rates are: @@ -36,8 +35,12 @@ To use the 61.44MHz clock rate, the USRP embedded will require two jumpers to be * J16 is a two pin header, remove the jumper (or leave it on pin1 only) * J15 is a three pin header, move the jumper to (pin1, pin2) -For the correct clock settings, call usrp->set_master_clock_rate(61.44e6) -before any other parameters are set in your application. +Then run the following commands to record the setting into the EEPROM: +:: + + cd <install-path>/share/uhd/utils + ./usrp_burn_mb_eeprom --key=mcr --val=61.44e6 + ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Set other rates - uses internal VCO @@ -47,8 +50,11 @@ To use other clock rates, the jumpers will need to be in the default position. * J16 is a two pin header, move the jumper to (pin1, pin2) * J15 is a three pin header, move the jumper to (pin2, pin3) -For the correct clock settings, call usrp->set_master_clock_rate(rate) -before any other parameters are set in your application. +Then run the following commands to record the setting into the EEPROM: +:: + + cd <install-path>/share/uhd/utils + ./usrp_burn_mb_eeprom --key=mcr --val=<rate> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Clock rate recovery - unbricking |