Merge branch 'next'

6 files changed, 66 insertions, 10 deletions

diff --git a/host/docs/CMakeLists.txt b/host/docs/CMakeLists.txt
index e393a79f0..f56358ca9 100644
--- a/host/docs/CMakeLists.txt
+++ b/host/docs/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2010-2011 Ettus Research LLC
+# Copyright 2010-2012 Ettus Research LLC
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -33,8 +33,8 @@ SET(manual_sources
     transport.rst
     usrp1.rst
     usrp2.rst
-    usrp_b1xx.rst
-    usrp_e1xx.rst
+    usrp_b100.rst
+    usrp_e1x0.rst
 )
 
 ########################################################################
diff --git a/host/docs/index.rst b/host/docs/index.rst
index 8649e7ce3..00b1c9618 100644
--- a/host/docs/index.rst
+++ b/host/docs/index.rst
@@ -25,9 +25,9 @@ Application Notes
 * `Firmware and FPGA Image Notes <./images.html>`_
 * `USRP1 Application Notes <./usrp1.html>`_
 * `USRP2 Application Notes <./usrp2.html>`_
-* `USRP-N2XX Series Application Notes <./usrp2.html>`_
-* `USRP-B1XX Series Application Notes <./usrp_b1xx.html>`_
-* `USRP-E1XX Series Application Notes <./usrp_e1xx.html>`_
+* `USRP-N2X0 Series Application Notes <./usrp2.html>`_
+* `USRP-B100 Series Application Notes <./usrp_b100.html>`_
+* `USRP-E1X0 Series Application Notes <./usrp_e1x0.html>`_
 * `Daughterboard Application Notes <./dboards.html>`_
 * `Transport Application Notes <./transport.html>`_
 * `Synchronization Application Notes <./sync.html>`_
diff --git a/host/docs/usrp1.rst b/host/docs/usrp1.rst
index 6242ccb6a..c1fdec146 100644
--- a/host/docs/usrp1.rst
+++ b/host/docs/usrp1.rst
@@ -5,6 +5,17 @@ UHD - USRP1 Application Notes
 .. contents:: Table of Contents
 
 ------------------------------------------------------------------------
+Comparative features list
+------------------------------------------------------------------------
+
+* 2 transceiver card slots
+* 2 RX DDC chains in FPGA
+* 2 TX DUC chains in FPGA (no TX CORDIC -> uses DAC)
+* 64 MHz fixed clock rate
+* sc16 sample modes
+* sc8 sample mode - RX only
+
+------------------------------------------------------------------------
 Specify a Non-standard Image
 ------------------------------------------------------------------------
 The standard USRP1 images installer comes with two FPGA images:
diff --git a/host/docs/usrp2.rst b/host/docs/usrp2.rst
index d70a08cd7..8e9aa6d50 100644
--- a/host/docs/usrp2.rst
+++ b/host/docs/usrp2.rst
@@ -1,10 +1,26 @@
 ========================================================================
-UHD - USRP2 and N Series Application Notes
+UHD - USRP2 and N2X0 Series Application Notes
 ========================================================================
 
 .. contents:: Table of Contents
 
 ------------------------------------------------------------------------
+Comparative features list
+------------------------------------------------------------------------
+
+* 1 transceiver card slot
+* 2 RX DDC chains in FPGA
+* 1 TX DUC chain in FPGA
+* Timed commands in FPGA (N2x0 only)
+* Timed sampling in FPGA
+* External PPS reference
+* External 10MHz reference
+* MIMO cable shared reference
+* Fixed 100 MHz clock rate
+* Internal GPSDO option (N2x0 only)
+* sc8 and sc16 sample modes
+
+------------------------------------------------------------------------
 Load the Images onto the SD card (USRP2 only)
 ------------------------------------------------------------------------
 **Warning!**
diff --git a/host/docs/usrp_b1xx.rst b/host/docs/usrp_b100.rst
index 08eeb441b..cdb853b61 100644
--- a/host/docs/usrp_b1xx.rst
+++ b/host/docs/usrp_b100.rst
@@ -1,10 +1,24 @@
 ========================================================================
-UHD - USRP-B1XX Series Application Notes
+UHD - USRP-B100 Series Application Notes
 ========================================================================
 
 .. contents:: Table of Contents
 
 ------------------------------------------------------------------------
+Comparative features list
+------------------------------------------------------------------------
+
+* 1 transceiver card slot
+* 1 RX DDC chain in FPGA
+* 1 TX DUC chain in FPGA
+* Timed commands in FPGA
+* Timed sampling in FPGA
+* External PPS reference
+* External 10MHz reference
+* Configurable clock rate (defaults 64 MHz)
+* sc8 and sc16 sample modes
+
+------------------------------------------------------------------------
 Specify a Non-standard Image
 ------------------------------------------------------------------------
 UHD will automatically select the USRP B-Series images from the installed images package.
diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1x0.rst
index 31a47347f..189cbb86b 100644
--- a/host/docs/usrp_e1xx.rst
+++ b/host/docs/usrp_e1x0.rst
@@ -1,10 +1,25 @@
 ========================================================================
-UHD - USRP-E1XX Series Application Notes
+UHD - USRP-E1X0 Series Application Notes
 ========================================================================
 
 .. contents:: Table of Contents
 
 ------------------------------------------------------------------------
+Comparative features list
+------------------------------------------------------------------------
+
+* 1 transceiver card slot
+* 2 RX DDC chains in FPGA
+* 1 TX DUC chain in FPGA
+* Timed commands in FPGA
+* Timed sampling in FPGA
+* Internal PPS reference
+* Internal 10MHz reference
+* Configurable clock rate (defaults 64 MHz)
+* Internal GPSDO option
+* sc8 and sc16 sample modes
+
+------------------------------------------------------------------------
 Specify a Non-standard Image
 ------------------------------------------------------------------------
 UHD will automatically select the USRP-Embedded FPGA image from the
@@ -115,7 +130,7 @@ The LEDs on the front panel can be useful in debugging hardware and software
 issues.  The LEDs reveal the following about the state of the device:
 
 * **LED A:** transmitting
-* **LED B:** fpga loaded
+* **LED B:** PPS signal
 * **LED C:** receiving
 * **LED D:** fpga loaded
 * **LED E:** reference lock