docs: Several minor manual improvements

- Remove documentation of skip_dram, skip_ddc, skip_duc, which are all
  obsolete since UHD 4
- Properly document serialize_init
- Add a table of valid args for X310 as with other devices

6 files changed, 49 insertions, 10 deletions

diff --git a/host/docs/configuration.dox b/host/docs/configuration.dox
index 48b8cea59..d9a121505 100644
--- a/host/docs/configuration.dox
+++ b/host/docs/configuration.dox
@@ -35,7 +35,7 @@ and possible more options.
  self_cal_adc_delay  | Run ADC transfer delay self-calibration.                                     | X3x0               | self_cal_adc_delay=1
  ext_adc_self_test   | Run an extended ADC self test (more than the usual)                          | X3x0               | ext_adc_self_test=1
  recover_mb_eeprom   | Disable version checks. Can damage hardware. Only recommended for recovering devices with corrupted EEPROMs. | X3x0 | recover_mb_eeprom=1
- skip_dram           | Ignore DRAM FIFO block. Connect TX streamers straight into DUC or radio.     | X3x0, N3xx         | skip_dram=1
+ serialize_init      | Force serial initialization of motherboards (default is parallel)            | X3x0, all MPM devices | serialize_init=1
 
 In addition, many of the streaming-related options can be set per-device at configuration time.
 See \ref config_stream_args and \ref page_transport for more details.
diff --git a/host/docs/multiple.dox b/host/docs/multiple.dox
index a401a22ad..ca768fa06 100644
--- a/host/docs/multiple.dox
+++ b/host/docs/multiple.dox
@@ -11,6 +11,8 @@ Currently, the following devices support this capability:
 
 - USRP2 / N2x0 Series
 - X3x0 Series
+- N3x0 Series
+- X4x0 Series
 
 Note that only USRPs of the same type can be combined.
 
diff --git a/host/docs/usrp_e3xx.dox b/host/docs/usrp_e3xx.dox
index 1b0cb4249..368cff34b 100644
--- a/host/docs/usrp_e3xx.dox
+++ b/host/docs/usrp_e3xx.dox
@@ -543,9 +543,6 @@ For a list of which arguments can be passed into make(), see Section
  addr                | IPv4 address of primary SFP+/RJ-45 port to connect to                         | addr=192.168.30.2
  find_all            | When using broadcast, find all devices, even if unreachable via CHDR.         | find_all=1
  master_clock_rate   | Master Clock Rate in Hz. Default is 16 MHz.                                   | master_clock_rate=30.72e6
- skip_dram           | Ignore DRAM FIFO block. Connect TX streamers straight into DUC or radio.      | skip_dram=1
- skip_ddc            | Ignore DDC block. Connect Rx streamers straight into radio.                   | skip_ddc=1
- skip_duc            | Ignore DUC block. Connect Tx streamers or DRAM straight into radio.           | skip_duc=1
  skip_init           | Skip the initialization process for the device.                               | skip_init=1
  discovery_port      | Override default value for MPM discovery port.                                | discovery_port=49700
  rpc_port            | Override default value for MPM RPC port.                                      | rpc_port=49701
diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox
index 82bffc105..2d2b84858 100644
--- a/host/docs/usrp_n3xx.dox
+++ b/host/docs/usrp_n3xx.dox
@@ -438,10 +438,7 @@ For a list of which arguments can be passed into make(), see Section
  force_reinit          | Force full reinitialization of all subsystems. Will increase init time.      | N310              | force_reinit=1
  master_clock_rate     | Master Clock Rate in Hz                                                      | N310              | master_clock_rate=125e6
  identify              | Causes front-panel LEDs to blink. The duration is variable.                  | N310              | identify=5 (will blink for about 5 seconds)
- serialize_init        | Force serial initialization of daughterboards.                               | All N3xx          | serialize_init=1
- skip_dram             | Ignore DRAM FIFO block. Connect TX streamers straight into DUC or radio.     | All N3xx          | skip_dram=1
- skip_ddc              | Ignore DDC block. Connect Rx streamers straight into radio.                  | All N3xx          | skip_ddc=1
- skip_duc              | Ignore DUC block. Connect Rx streamers or DRAM straight into radio.          | All N3xx          | skip_duc=1
+ serialize_init        | Force serial initialization of motherboards.                                 | All N3xx          | serialize_init=1
  skip_init             | Skip the initialization process for the device.                              | All N3xx          | skip_init=1
  time_source           | Specify the time (PPS) source.                                               | All N3xx          | time_source=internal
  clock_source          | Specify the reference clock source.                                          | All N3xx          | clock_source=internal
@@ -473,6 +470,8 @@ clock_source=external
 
 If you prefer not to have the device initialize on boot, but rather have a fast
 boot time, add the line `skip_boot_init=1` to your `/etc/uhd/mpm.conf` file.
+This will force a full initialization of the device the first time a UHD session
+is started, rather than during device boot.
 
 For more details on the initialization sequence, see the corresponding section
 for the specific N3XX device:
@@ -1062,6 +1061,11 @@ clock_source=external
 If you prefer not to have the device initialize on boot, but rather have a fast
 boot time, add the line `skip_boot_init=1` to your `/etc/uhd/mpm.conf` file.
 
+If there are multiple N3x0 devices in a single UHD session, they will be
+initialized in parallel. Note that this behaviour can be changed serial
+initialization by adding `serialize_init=1` to the device args
+(see \ref n3xx_usage_device_args).
+
 \subsection n3xx_mg_calibrations RF Calibrations
 
 The onboard RFIC (AD9371) has built-in calibrations which can be enabled from
diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox
index c95ddd1b9..45254c9d9 100644
--- a/host/docs/usrp_x3x0.dox
+++ b/host/docs/usrp_x3x0.dox
@@ -105,6 +105,41 @@ When your FPGA is up to date, power-cycle the device and re-run `uhd_usrp_probe`
 be no more warnings at this point, and all components should be correctly detected. Your USRP is now
 ready for development!
 
+
+\section x3x0_usage Using an X3X0 USRP from UHD
+
+Like any other USRP, all X3X0 USRPs are controlled by the UHD software. To
+integrate a USRP X3X0 into your C++ application, you would generate a UHD
+device in the same way you would for any other USRP:
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~{.cpp}
+auto usrp = uhd::usrp::multi_usrp::make("type=x300");
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+For a list of which arguments can be passed into make(), see Section
+\ref x3x0_usage_device_args.
+
+\subsection x3x0_usage_device_args Device arguments
+
+ Key                   | Description                                                      |  Example Value
+-----------------------|------------------------------------------------------------------|----------------------
+ addr                  | IPv4 address of primary SFP+ port to connect to                  |  addr=192.168.30.2
+ second_addr           | IPv4 address of secondary SFP+ port to connect to                |  second_addr=192.168.40.2
+ resource              | NI-RIO resource                                                  |  resource=RIO0
+ master_clock_rate     | Master Clock Rate in Hz (see \ref x3x0_set_clocking_mboard)      |  master_clock_rate=184.32e6
+ dboard_clock_rate     | Daughterboard Clock Rate in Hz                                   |  dboard_clock_rate=50e6
+ system_ref_rate       | Frequency of external reference/clock signal in Hz (see \ref x3x0_hw_x3x0_hw_ref10M) |  system_ref_rate=30.72e6
+ serialize_init        | Force serial initialization of motherboards (default: initialize in parallel) |  serialize_init=1
+ time_source           | Specify the time (PPS) source                                    |  time_source=external
+ clock_source          | Specify the reference clock source                               |  clock_source=external
+ self_cal_adc_delay    | Run ADC transfer delay self-calibration routine                  |  self_cal_adc_delay=1
+ ext_adc_self_test     | Run extended ADC self-test (excludes self_cal_adc_delay)         |  ext_adc_self_test=1
+ ext_adc_self_test_duration | Duration of extended ADC self-test (default: 30s)           |  ext_adc_self_test_duration=60
+ recover_mb_eeprom     | Enable EEPROM recovery, disable HW revision checks (see \ref x3x0_corrupt_eeprom) | recover_mb_eeprom=1
+ use_dpdk              | Use DPDK (see \ref page_dpdk)                                    |  use_dpdk=1
+ fpga                  | Choose FPGA image to run (only works over PCIe)                  |  fpga=/path/to/bitfile.lvbitx
+ fw                    | Load custom firmware image                                       |  fw=/path/to/hw.bin
+
 \section x3x0_hw Hardware Setup
 
 \subsection x3x0_hw_1gige Gigabit Ethernet (1 GigE)
@@ -452,7 +487,8 @@ available to the application can be 200 Msps, 100 Msps, 66.6 Msps, 50 Msps, and
 so on.
 
 The X300 series support a 200 MHz and a 184.32 MHz master clock rate, with
-200 MHz being the default. To specify a master clock rate, use the
+200 MHz being the default (when using TwinRX, only 200 MHz is available). To
+specify a master clock rate, use the
 `master_clock_rate` device arg at initialization time. Example:
 ~~~{.cpp}
 auto usrp = uhd::usrp::multi_usrp::make("type=x300,master_clock_rate=184.32e6");
diff --git a/host/docs/usrp_x4xx.dox b/host/docs/usrp_x4xx.dox
index fa05c7b4c..8fd555593 100644
--- a/host/docs/usrp_x4xx.dox
+++ b/host/docs/usrp_x4xx.dox
@@ -792,7 +792,7 @@ For a list of which arguments can be passed into make(), see Section
  mgmt_addr             | IPv4 address or hostname to which to connect the RPC client. Defaults to `addr'.| mgmt_addr=ni-sulfur-311FE00
  find_all              | When using broadcast, find all devices, even if unreachable via CHDR.           | find_all=1
  master_clock_rate     | Master Clock Rate in Hz.                                                        | master_clock_rate=250e6
- serialize_init        | Force serial initialization of daughterboards.                                  | serialize_init=1
+ serialize_init        | Force serial initialization of motherboards (default is parallel)               | serialize_init=1
  skip_init             | Skip the initialization process for the device.                                 | skip_init=1
  time_source           | Specify the time (PPS) source.                                                  | time_source=internal
  clock_source          | Specify the reference clock source.                                             | clock_source=internal