Merge branch 'maint'

2 files changed, 22 insertions, 2 deletions

diff --git a/host/docs/usrp_e3x0.dox b/host/docs/usrp_e3x0.dox
index f711c4a37..cc2b99945 100644
--- a/host/docs/usrp_e3x0.dox
+++ b/host/docs/usrp_e3x0.dox
@@ -437,7 +437,8 @@ For more advanced IMU based applications please refer to the <a href="https://gi
 
 Please see the \ref page_gpio_api for information on configuring and using the GPIO bus.
 
-\subsection e3x0_hw_audio Audio connectors
+\subsection e3x0_hw_audio Audio connectors (if populated)
+
 The E3x0 2.5 mm Audio Jack TRRS pins are assigned as follows: Tip=Mic, Ring1=Right, Ring2=Left, Sleeve=GND. 
 
 \image html TRRS.png "Audio Jack"
@@ -545,6 +546,22 @@ Both transmit and receive can be used in a MIMO configuration. For
 the MIMO case, both receive frontends share the RX LO, and both transmit
 frontends share the TX LO. Each LO is tunable between 50 MHz and 6 GHz.
 
+As there is a single LO for each direction (RX and TX), this means that both
+channels need to use the same LO frequency (i.e., both RX channels share an LO
+frequency, and both TX channels share an LO frequency). If the two channels
+are supposed to receive on different frequencies, the digital tune stages need
+to be used for that. The two frequencies will need to be within the currently
+selected master clock rate, and the final bandwidths need to be chosen
+carefully. Example: Assume the master clock rate is set to 50 MHz, and we want
+to receive at 400 MHz and 440 MHz. We can set the LO to 420 MHz, which will
+sample the spectrum from 395 MHz to 445 MHz. The LO offsets for both channels
+need to be 20 MHz and -20 MHz respectively. However, the final bandwidth should
+be less than 10 MHz (preferably lower), or the signals would exhibit aliasing.
+
+Because both channels share an LO, tuning one channel can possibly affect the
+other channel. It is advisable to read back the actual, current frequency from
+software before assuming the device is tuned to a specific frequency.
+
 \subsubsection e3x0_dboard_e310_gain Frontend gain
 
 All frontends have individual analog gain controls. The receive
diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox
index 48f319407..d76d5eaa0 100644
--- a/host/docs/usrp_x3x0.dox
+++ b/host/docs/usrp_x3x0.dox
@@ -442,7 +442,10 @@ for information specific to certain daughterboards.
 
 Not all combinations of daughterboards work within the same device, if
 daughterboard clock requirements conflict. Note that some daughterboards
-(e.g. the UBX) will try and set the daughterboard clock rate themselves.
+will try and set the daughterboard clock rate themselves. Refer to the
+<a href="https://kb.ettus.com/X300/X310#Choosing_an_RF_Daughterboard">Ettus Research
+Knowledge Base article on the X300/X310</a> for more information on daughterboard
+compatibilty.
 
 \section x3x0_addressing Addressing the Device