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| author | Andrej Rode <andrej.rode@ettus.com> | 2017-02-17 18:47:57 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-02-20 11:57:24 -0800 |
| commit | 784337d946b5461e4660f4f4cf70624882bba8bc (patch) | |
| tree | 391122a1f75733b75c17ab32846dcaae141973fa /host/docs | |
| parent | e256f3db52535b4b03086c5f7e0c8aed178e322b (diff) | |
| download | uhd-784337d946b5461e4660f4f4cf70624882bba8bc.tar.gz uhd-784337d946b5461e4660f4f4cf70624882bba8bc.tar.bz2 uhd-784337d946b5461e4660f4f4cf70624882bba8bc.zip | |
docs: escape /* to silence doxygen while compiling
Diffstat (limited to 'host/docs')
| -rw-r--r-- | host/docs/rd_testing.dox | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/host/docs/rd_testing.dox b/host/docs/rd_testing.dox index a77ec29c5..923cfa573 100644 --- a/host/docs/rd_testing.dox +++ b/host/docs/rd_testing.dox @@ -162,18 +162,18 @@ These tests are simulations and do not need any device. Vivado 15.4 should be in 1. Go to the fpga directory depending on which test needs to be run. 1. NoC block test benches: - Most of the NoC blocks have a test bench written in System Verilog that provides stimuli to the noc_block to verify it. The test bench for a block resides in <fpga-dir>/usrp3/lib/rfnoc/*_tb. + Most of the NoC blocks have a test bench written in System Verilog that provides stimuli to the noc_block to verify it. The test bench for a block resides in `<fpga-dir>/usrp3/lib/rfnoc/‍*_tb`. 2. Running unit test benches: - A few sub-blocks like noc-shell and sine_tone are used within the bigger noc_blocks. They have their own test benches. Their test benches reside in <fpga-dir>/usrp3/lib/sim/rfnoc/*. + A few sub-blocks like noc-shell and sine_tone are used within the bigger noc_blocks. They have their own test benches. Their test benches reside in `<fpga-dir>/usrp3/lib/sim/rfnoc/‍*`. 3. Radio test bench: - The radio test bench resides in <fpga-dir>/usrp3/lib/radio/noc_block_radio_core_tb/. + The radio test bench resides in `<fpga-dir>/usrp3/lib/radio/noc_block_radio_core_tb/`. 4. Device specific test benches: - IPs specific to a device have test benches that exist in <fpga-dir>/usrp3/top/x300/sim/*. e.g. DMA testbench, PCIe, etc. + IPs specific to a device have test benches that exist in `<fpga-dir>/usrp3/top/x300/sim/*`. e.g. DMA testbench, PCIe, etc. -2. Setup the environment by running 'source <fpga-dir>/usrp3/top/<device>/setupenv.sh'. +2. Setup the environment by running `source <fpga-dir>/usrp3/top/<device>/setupenv.sh`. 3. In the test bench directory and run the test bench by 'make xsim' or 'make vsim'. |