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author | Martin Braun <martin.braun@ettus.com> | 2016-09-26 16:24:48 -0700 |
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committer | Martin Braun <martin.braun@ettus.com> | 2016-10-13 17:10:20 -0700 |
commit | 3e65841e5bcd643a9f390ddae003d48db9e784f4 (patch) | |
tree | 07ccbf31f483648c1e65202f78a9b0c40595aa3b /host/docs | |
parent | 8d9ae5b37b4f0c5339fffc138332c9afdf65b11d (diff) | |
download | uhd-3e65841e5bcd643a9f390ddae003d48db9e784f4.tar.gz uhd-3e65841e5bcd643a9f390ddae003d48db9e784f4.tar.bz2 uhd-3e65841e5bcd643a9f390ddae003d48db9e784f4.zip |
docs: Added some info on X3x0 dboard_clock_rate and which dboards need to set it.
Diffstat (limited to 'host/docs')
-rw-r--r-- | host/docs/dboards.dox | 28 | ||||
-rw-r--r-- | host/docs/usrp_x3x0.dox | 15 |
2 files changed, 43 insertions, 0 deletions
diff --git a/host/docs/dboards.dox b/host/docs/dboards.dox index 2ce6c4563..4f2b22825 100644 --- a/host/docs/dboards.dox +++ b/host/docs/dboards.dox @@ -101,6 +101,9 @@ Sensors: - **lo_locked**: boolean for LO lock state +Notes: +- When used in the X3x0, set the daughterboard clock rate to 100 MHz (see \ref config_devaddr) + \subsection dboards_rfx RFX Series The RFX Series boards have 2 quadrature frontends: Transmit and Receive. @@ -343,6 +346,12 @@ LEDs: - **TX/RX RXD**: Receiving on TX/RX antenna port - **RX2 RXD**: Receiving on RX2 antenna port + +Notes: +- When used in the X300/X310 at frequencies below 1 GHz, it is necessary to + reduce the daughterboard clock rate to 20 MHz to achieve phase + synchronization and best RF performance (see \ref config_devaddr). + \subsection dboards_tvrx TVRX The TVRX board has 1 real-mode frontend. It is operated at a low IF. @@ -384,10 +393,29 @@ Sensors: - **rssi**: float for measured RSSI in dBm - **temperature**: float for measured temperature in degC +Notes: + +- The TVRX2 requires a 64 MHz, 100 MHz or 200 MHz reference clock. On the X3x0, + set the daughterboard clock rate accordingly (see \ref config_devaddr), typically + to 100 MHz. + \subsection dboards_e300 E310 MIMO XCVR board Please refer to \ref e3x0_dboard_e310. + +\subsection dboards_clock_rate Daughterboard reference clock + +The USRP motherboard provides a reference clock to the daughterboards, which +the daughterboards will use to generate LO signals or anything else that +requires a reference clock. + +The X3x0 has a programmable reference clock, which might have to be changed +depending on various applications (see the daughterboard sections above). +However, it can provide only one daughterboard clock per device, which can +lead to conflicts. It might not be possible to use a specific daughterboard +together with all others. + \subsection dboards_dbsrxmod DBSRX - Modifying for other boards that USRP1 Due to different clocking capabilities, the DBSRX will require diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox index db19ca551..5f7284a09 100644 --- a/host/docs/usrp_x3x0.dox +++ b/host/docs/usrp_x3x0.dox @@ -18,6 +18,7 @@ More information: - External 10 MHz input & output - Expandable via 2nd SFP+ interface - Supported master clock rates: 200 MHz and 184.32 MHz + - Variable daughterboard clock rates - External GPIO Connector with UHD API control - External USB Connection for built-in JTAG debugger - Internal GPSDO option @@ -430,6 +431,20 @@ Run the following commands: You must power-cycle the device before you can use this new address. +\section x3x0_setup_clocking Setup Clocking + +\subsection x3x0_set_clocking_dboard Daughterboard clock + +The X3x0 provides a clock signal to the daughterboards which is used as a +reference clock for synthesizers and other components that require clocks. +There are daughterboards that require non-default clock values. See +Section \ref config_devaddr on how to change the clock value, and \ref page_dboards +for information specific to certain daughterboards. + +Not all combinations of daughterboards work within the same device, if +daughterboard clock requirements conflict. Note that some daughterboards +(e.g. the UBX) will try and set the daughterboard clock rate themself. + \section x3x0_addressing Addressing the Device \subsection x3x0_addressing_singledev Single device configuration |