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authorMartin Braun <martin.braun@ettus.com>2019-02-26 16:20:48 -0800
committerBrent Stapleton <brent.stapleton@ettus.com>2019-02-28 11:52:21 -0800
commit333df1de86883d81552323ea147d74fa7374792a (patch)
tree7d418fade58e218fb17dac3dc81a58b8938fd375 /host/docs/usrp_x3x0.dox
parent0592032f4a3aba7feafdcba017b1df42457c1d37 (diff)
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docs: x300: Add notes on external reference frequencies
Diffstat (limited to 'host/docs/usrp_x3x0.dox')
-rw-r--r--host/docs/usrp_x3x0.dox13
1 files changed, 11 insertions, 2 deletions
diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox
index e8d1af24e..d55643e1f 100644
--- a/host/docs/usrp_x3x0.dox
+++ b/host/docs/usrp_x3x0.dox
@@ -15,7 +15,7 @@ More information:
- Dual SFP+ Transceivers (can be used with 1 GigE, 10 GigE)
- PCI Express over cable (MXI) gen1 x4
- External PPS input & output
- - External 10 MHz input & output
+ - External reference (10 MHz, 11.52 MHz, 23.04 MHz, or 30.72 MHz) input & output
- Expandable via 2nd SFP+ interface
- Supported master clock rates: 200 MHz and 184.32 MHz
- Variable daughterboard clock rates
@@ -663,12 +663,21 @@ Afterward, power-cycle your X-Series device for the changes to take effect.
- **PPS/TRIG IN**: Input port for the PPS signal
- **GPS**: Connection for the GPS antenna
-\subsection x3x0_hw_x3x0_hw_ref10M Ref Clock - 10 MHz
+\subsection x3x0_hw_x3x0_hw_ref10M Ref Clock (10 MHz or other frequency)
Using an external 10 MHz reference clock, a square wave will offer the best phase
noise performance, but a sinusoid is acceptable.
The power level of the reference clock must exceed +15 dBm.
+The following reference frequencies are supported:
+- 10 MHz
+- 11.52 MHz
+- 23.04 MHz
+- 30.72 MHz
+
+If the external reference clock is not 10 MHz, the `system_ref_rate` device arg
+must be provided.
+
To use the external reference in your UHD session, make sure to either call
uhd::usrp::multi_usrp::set_clock_source() or specify `clock_source=external` in
your device args.