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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-08-10 23:14:20 -0700 |
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| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-08-10 23:14:20 -0700 |
| commit | b5c81677078f56b3e671ebeaca1e3b803c2f4ef9 (patch) | |
| tree | a1b17b4be203331de7e146e94051f26be5a20102 /host/docs/usrp_x3x0.dox | |
| parent | 16e149fe6fcc1bc18adea3eeeefad2c7ee93b2e0 (diff) | |
| parent | 28327c8e8a810b19da126116d0dc4c26b643baed (diff) | |
| download | uhd-b5c81677078f56b3e671ebeaca1e3b803c2f4ef9.tar.gz uhd-b5c81677078f56b3e671ebeaca1e3b803c2f4ef9.tar.bz2 uhd-b5c81677078f56b3e671ebeaca1e3b803c2f4ef9.zip | |
Merge branch 'master' into ashish/register_api
Diffstat (limited to 'host/docs/usrp_x3x0.dox')
| -rw-r--r-- | host/docs/usrp_x3x0.dox | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/host/docs/usrp_x3x0.dox b/host/docs/usrp_x3x0.dox index 7183efc04..bf2323b71 100644 --- a/host/docs/usrp_x3x0.dox +++ b/host/docs/usrp_x3x0.dox @@ -609,6 +609,30 @@ The +3.3V is for ESD clamping purposes only and not designed to deliver high cur Please see the \ref page_gpio_api for information on configuring and using the GPIO bus. +\subsection x3x0_hw_on_board_leds On-Board LEDs + +|LED | | Description | +|-------|---------------|-------------------------------| +|DS1 |1.2V |power | +|DS2 |TXRX1 |Red: TX, Green: RX | +|DS3 |RX1 |Green: RX | +|DS4 |REF |reference lock | +|DS5 |PPS |flashes on edge | +|DS6 |GPS |GPS lock | +|DS7 |SFP0 |link | +|DS8 |SFP0 |link activity | +|DS10 |TXRX2 |Red: TX Green: RX | +|DS11 |RX2 |Green: RX | +|DS12 |6V |daughterboard power | +|DS13 |3.8V |power | +|DS14 |3.3V |management power | +|DS15 |3.3V |auxiliary management power | +|DS16 |1.8V |FPGA power | +|DS16 |3.3V |FPGA power | +|DS19 |SFP1 |link | +|DS20 |SFP1 |link active | +|DS21 |LINK |link activity | + \subsection x3x0_hw_chipscope Debugging custom FPGA designs with Xilinx Chipscope Xilinx chipscope allows for debugging custom FPGA designs similar to a logic analyzer. |