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| author | Martin Braun <martin.braun@ettus.com> | 2018-07-24 15:03:33 -0700 |
|---|---|---|
| committer | Brent Stapleton <brent.stapleton@ettus.com> | 2018-07-31 10:05:03 -0700 |
| commit | bd6ac34de76e7415cd0c6dc535babd8a58d73185 (patch) | |
| tree | 745ed643864b6846da803e8629cb45fb552159d2 /host/docs/usrp_n3xx.dox | |
| parent | ab1c74c7e4cc7f0fa339be7b6685109045f6f878 (diff) | |
| download | uhd-bd6ac34de76e7415cd0c6dc535babd8a58d73185.tar.gz uhd-bd6ac34de76e7415cd0c6dc535babd8a58d73185.tar.bz2 uhd-bd6ac34de76e7415cd0c6dc535babd8a58d73185.zip | |
docs: Fix Doxygen warnings
Diffstat (limited to 'host/docs/usrp_n3xx.dox')
| -rw-r--r-- | host/docs/usrp_n3xx.dox | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/docs/usrp_n3xx.dox b/host/docs/usrp_n3xx.dox index 482a97e44..eb412a020 100644 --- a/host/docs/usrp_n3xx.dox +++ b/host/docs/usrp_n3xx.dox @@ -791,7 +791,7 @@ the initialization sequence, the following steps are performed: - All clocking is initialized - The JESD links are trained and brought up (between the FPGA and the AD9371) - The AD9371 is reset, its firmware is uploaded, and calibrations are - initialized (See also \section n3xx_mg_calibrations) + initialized (See also \ref n3xx_mg_calibrations) - N310 only: The multi-chip synchronization is performed to align all the RFICs to the common time and clock reference |